IP Library Granted Patent US 10,121,848
Granted Patent B2
US 10,121,848 · App. 15/594,653 · Granted Nov 6, 2018

Method for manufacturing multilayer crown-shaped MIM capacitor

Inventors: Shyng-Yeuan Che (Hsinchu County, TW); Wen-Yi Wong (Kinmen County, TW)
Assignee: Powerchip Technology Corporation
H01L28/75H01L28/60H01L21/76877H01L29/66181
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Quick Facts
Patent No.
US 10,121,848
App. No.
15/594,653
Granted
Nov 6, 2018
Kind
B2
Abstract

A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.

Claims (13)

1. A method for fabricating a multi-layer, crown-shaped metal-insulator-metal (MIM) capacitor, comprising:

providing a base having therein a conductive region disposed within a capacitor-forming region;

depositing an inter-metal dielectric (IMD) layer on the base and covering the capacitor-forming region;

forming a capacitor trench within the capacitor-forming region, the capacitor trench penetrating through the IMD layer, thereby exposing a portion of the conductive region;

forming a concentric capacitor lower electrode structure within the capacitor trench, the concentric capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, wherein the first electrode is in direct contact with the conductive region;

forming a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes, wherein the conductive supporting pedestal comprising an inner portion situated at the bottom portion of the second electrode and an annular outer portion situated between the first electrode and the second electrode, and wherein the inner portion is not in direct contact with the annular outer portion;

forming a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal; and

forming a capacitor upper electrode on the capacitor dielectric layer.

2. The method for fabricating a multi-layer, crown-shaped MIM capacitor according to claim 1 , wherein before forming the capacitor trench in the IMD layer, a metal interconnection structure is formed within the IMD layer outside the capacitor-forming region.

3. The method for fabricating a multi-layer, crown-shaped MIM capacitor according to claim 1 , wherein the capacitor upper electrode fills up a gap between the first lower electrode and the second lower electrode.

4. The method for fabricating a multi-layer, crown-shaped MIM capacitor according to claim 3 , wherein the capacitor upper electrode comprises copper, aluminum, titanium, titanium nitride, or tungsten.

5. The method for fabricating a multi-layer, crown-shaped MIM capacitor according to claim 1 , wherein the first lower electrode and the second lower electrode comprise titanium or titanium nitride.

6. The method for fabricating a multi-layer, crown-shaped MIM capacitor according to claim 5 , wherein the conductive supporting pedestal comprises tungsten.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049770/0199 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2017
From: CHE, SHYNG-YEUAN; WONG, WEN-YI
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 042370/0036 →
Priority Claims (1)
TW 104129610 A · Sep 8, 2015 · national
Continuity (2)
Division 14986717 · Jan 3, 2016
Related Publication 20170250245A1 · Aug 31, 2017