IP Library › Patent Application 15594765

Patent Application

App. No. 15/594,765

DISPLAY PANEL, SHIFT REGISTER CIRCUIT AND DRIVING METHOD THEREOF

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Patent No.: US None
App. No.: 15/594,765

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Abstract

A display panel, a shift register circuit, and a driving method of the shift register circuit are provided. The shift register circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. When turned on individually, the first transistor provides an input signal to a second node, the second transistor provides the input signal to the first node, the third transistor provides a charging signal to a second node, the fourth transistor provides a first voltage signal to a third node, the fifth transistor provides a voltage signal at the third node to the first node, the sixth transistor provides the first voltage signal to a signal output terminal, and the seventh transistor provides the second clock signal to the signal output terminal.

Claims (72)

1 . A shift register circuit, comprising:

a first transistor, configured to be turned on in response to a voltage signal at a first node, such that an input signal is provided to a second node;

a second transistor, configured to be turned on in response to a first clock signal, such that the input signal is provided to the first node;

a third transistor, configured to be turned on in response to the first clock signal, such that a charging signal is provided to a second node;

a fourth transistor, configured to be turned on in response to a voltage signal at the second node, such that a first voltage signal is provided to a third node;

a fifth transistor, configured to be turned on in response to a second clock signal, such that a voltage signal at the third node is provided to the first node;

a sixth transistor, configured to be turned on in response to the voltage signal at the second node, such that the first voltage signal is provided to a signal output terminal;

a seventh transistor, configured to be turned on in response to a voltage signal at a fourth node, such that the second clock signal is provided to the signal output terminal, wherein a voltage at the fourth node is positively correlated to a voltage at the first node;

a first capacitor electrically connected between the fourth node and the signal output terminal; and

a second capacitor electrically connected between the second node and the first voltage signal.

2 . The shift register circuit according to claim 1 , wherein:

the first transistor to the seventh transistor each has a first end, a second end, and a control end;

a control end of the first transistor is electrically connected to the first node, a first end of the first transistor receives an input signal, and a second end of the first transistor is electrically connected to the second node;

a control end of the second transistor receives the first clock signal, a first end of the second transistor receives the input signal, and a second end of the second transistor is electrically connected to the first node;

a control end of the third transistor receives the first clock signal, a first end of the third transistor receives the charging signal, and a second end of the third transistor is electrically connected to the second node;

a control end of the fourth transistor is electrically connected to the second node, and a first end of the fourth transistor receives the first voltage signal;

a control end of the fifth transistor receives the second clock signal, a first end of the fifth transistor is electrically connected to a second end of the fourth transistor, and a second end of the fifth transistor is electrically connected to the first node;

a control end of the six transistor is electrically connected to the second node, a first end of the sixth transistor receives the first voltage signal, and a second end of the sixth transistor is electrically connected to the signal output terminal; and

a control end of the seventh transistor is electrically connected to the fourth node, a first end of the seventh transistor receives the second clock signal, and a second end of the seventh transistor is electrically connected to the signal output terminal.

3 . The shift register circuit according to claim 1 , wherein:

the first transistor to the seventh transistor each has a first end, a second end, and a control end;

a control end of the first transistor is electrically connected to the first node, a first end of the first transistor receives the input signal, and a second end of the first transistor is electrically connected to the second node;

a control end of the fourth transistor is electrically connected to the second node, and a first end of the fourth transistor is electrically connected to the signal output terminal;

a control end of the seventh transistor is electrically connected to the first node, a first end of the seventh transistor receives the second clock signal, and a second end of the seventh transistor is electrically connected to the signal output terminal.

4 . The shift register circuit according to claim 1 , wherein:

the first node and the fourth node are a same node.

5 . The shift register circuit according to claim 1 , further comprising:

an eighth transistor, configured to be turned on in response to a second voltage signal, wherein the eighth transistor is electrically connected between the first node and the fourth node.

6 . The shift register circuit according to claim 1 , wherein:

the charging signal is the second voltage signal.

7 . The shift register circuit according to claim 1 , wherein:

the charging signal is the second clock signal.

8 . The shift register circuit according to claim 5 , wherein:

all the transistors are P-type transistors.

9 . The shift register circuit according to claim 5 , wherein:

all the transistors are N-type transistors.

10 . The shift register circuit according to claim 5 , wherein:

the first voltage signal is a high voltage level signal, and the second voltage signal is a low voltage level signal; or

the first voltage signal is a low voltage level signal, and the second voltage signal is a high voltage level signal.

11 . The shift register circuit according to claim 5 , wherein:

the first voltage signal is a high voltage level signal, and the second voltage signal is a low voltage level signal; or

the first voltage signal is a low voltage level signal, and the second voltage signal is a high voltage level signal.

12 . The shift register circuit according to claim 1 , wherein:

low voltage duty cycles of the first clock signal and the second clock signal are both lower than ½, and the first clock signal and the second clock signal are differed by ½ signal cycle; or

high voltage duty cycles of the first clock signal and the second clock signal are both lower than ½, and the first clock signal and the second clock signal are differed by ½ signal cycle.

13 . A driving method of a shift register circuit, wherein the shift register circuit comprises a first transistor configured to be turned on in response to a voltage signal at a first node to provide an input signal to a second node, a second transistor configured to be turned on in response to a first clock signal to provide the input signal to the first node, a third transistor configured to be turned on in response to the first clock signal to provide a charging signal to a second node, a fourth transistor configured to be turned on in response to a voltage signal at the second node to provide a first voltage signal to a third node, a fifth transistor configured to be turned on in response to a second clock signal to provide a voltage signal at the third node to the first node, a sixth transistor configured to be turned on in response to the voltage signal at the second node to provide the first voltage signal to a signal output terminal, a seventh transistor configured to be turned on in response to a voltage signal at a fourth node to provide the second clock signal to the signal output terminal, a first capacitor electrically connected between the fourth node and the signal output terminal, and a second capacitor electrically connected between the second node and the first voltage signal, and a voltage at the fourth node is positively correlated to a voltage at the first node, the driving method comprising:

in a first stage, controlling, by the first clock signal, the input signal and the first voltage signal, the second transistor, the third transistor, and the seventh transistor to be turned off, controlling, by the second clock signal, the fifth transistor to be turned on, and transmitting, by the sixth transistor, the first voltage signal to the signal output terminal.

14 . The driving method according to claim 13 , further comprising:

in a second stage, controlling, by the first clock signal and the input signal, the first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor, and the seventh transistor to be turned on, controlling, by the second clock signal, the fifth transistor to be turned off, and transmitting, by the sixth transistor, the first voltage signal to the signal output terminal; and

in a third stage, controlling, by the first clock signal and the input signal, the second transistor, the third transistor, the fourth transistor, and the sixth transistor to be turned off, controlling, by the second clock signal, the fifth transistor to be turned on, and transmitting, by the seventh transistor, the second voltage signal to the signal output terminal.

15 . The driving method according to claim 13 , further comprising:

in a fourth stage, controlling, by the first clock signal, the second transistor and the third transistor to be turned on, controlling, by the input signal and the second clock signal, the first transistor, the seventh transistor and the fifth transistor to be turned off, and transmitting, by the sixth transistor, the first voltage signal to the signal output terminal; and

in a fifth stage, controlling, by the first clock signal and the input signal control, the second transistor, the third transistor, the first transistor, and the seventh transistor to be turned off, controlling, by the second clock signal, the fifth transistor to be turned on, and transmitting, by the sixth transistor, the first voltage signal to the signal output terminal.

16 . A display panel including a shift register circuit, wherein the shift register circuit comprises: