Nonvolatile memory device having resistive memory cells including at least one resistive memory cell initial state

1. A nonvolatile memory device, comprising:

a plurality of resistive memory cells each of which takes either a variable state or an initial state, the plurality of resistive memory cells including a memory group including at least one resistive memory cell in the initial state; and

a read circuit comprising a resistance detection circuit that obtains resistance value information of the plurality of resistive memory cells, and a data generation circuit that generates digital data corresponding to the resistance value information obtained by the resistance detection circuit, wherein

the resistance detection circuit comprises a voltage application circuit that selectively applies a first read voltage for reading a resistive memory cell in the variable state, and a second read voltage that is larger than the first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state, and

in order to obtain resistance value information of the at least one resistive memory cell in the initial state, the voltage application circuit applies the second read voltage to the at least one resistive memory cell in the initial state, and after the second read voltage is applied to the at least one resistive memory cell in the initial state, the at least one resistive memory cell maintains the initial state.

2. The nonvolatile memory device according to claim 1 , wherein:

the plurality of resistive memory cells include a first memory group including a plurality of resistive memory cells in the variable state, and the memory group as a second memory group,

the read circuit further comprises a voltage setting circuit that, in order to obtain the resistance value information of the at least one resistive memory cell in the initial state of the second memory group, sets a voltage that is applied to the at least one resistive memory cell in the initial state of the second memory group by the voltage application circuit to be the second read voltage, and in order to obtain resistance value information of the plurality of resistive memory cells of the first memory group, sets a voltage that is applied to the plurality of resistive memory cells of the first memory group by the voltage application circuit to be the first read voltage,

in each of the plurality of resistive memory cells in the variable state, a resistance value reversibly transitions between a plurality of variable resistance value ranges when voltage pulses of different polarities are applied, and

in each of the at least one resistive memory cell in the initial state, a resistance value is in an initial resistance value range that does not overlap with the variable resistance value ranges.

3. The nonvolatile memory device according to claim 1 , wherein

the memory group includes a plurality of resistive memory cells in the initial state.

4. The nonvolatile memory device according to claim 3 , wherein

the data generation circuit generates first security data by mutually comparing resistance value information of the plurality of resistive memory cells included in the memory group.

5. The nonvolatile memory device according to claim 3 , further comprising a determination value generation circuit that generates a determination value by using resistance value information of the plurality of resistive memory cells of the memory group, wherein

the data generation circuit uses the determination value to generate first security data corresponding to the resistance value information of the at least one resistive memory cell in the initial state.

6. The nonvolatile memory device according to claim 5 , wherein

the determination value is a binarization reference value.

7. The nonvolatile memory device according to claim 1 , wherein

the at least one resistive memory cell in the initial state is half or more of all resistive memory cells included in the memory group.

8. The nonvolatile memory device according to claim 2 , wherein

the variable state includes a first resistance state and a second resistance state having a higher resistance value than that of the first resistance state, and

a resistance value in the initial state is higher than the resistance value in the second resistance state.

9. The nonvolatile memory device according to claim 8 , wherein

data are recorded in the first memory group by using the first resistance state and the second resistance state, and

second security data are recorded in the second memory group by using the variable state and the initial state.

10. The nonvolatile memory device according to claim 9 , wherein

first security data are recorded in the second memory group.

11. The nonvolatile memory device according to claim 9 , wherein

third security data that is encrypted using the first security data is recorded in the second memory group.

12. The nonvolatile memory device according to claim 2 , wherein each of the at least one resistive memory does not change a state from the initial state to the variable state unless the forming pulse is applied.

13. A nonvolatile memory device, comprising:

a plurality of resistive memory cells each of which takes either a variable state or an initial state, the plurality of resistive memory cells including at least one resistive memory cell in the initial state; and

a read circuit comprising a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell in the initial state, and a data generation circuit that generates digital data corresponding to the resistance value information obtained by the resistance detection circuit, wherein:

the resistance detection circuit applies a second read voltage to the at least one resistive memory cell in the initial state in order to obtain the resistance value information based on the second read voltage, the second read voltage being larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state, the first read voltage being for reading a resistive memory cell in the variable state, and

after the second read voltage is applied to the at least one resistive memory cell in the initial state, the at least one resistive memory cell maintains the initial state.