Display apparatus and display apparatus control circuit
View Patent ↗A display apparatus includes: a display device; a display device driver which drives the display device; a compression section adapted to an operation of generating compression data by compression processing performed on image data; and a transmission section which, when receiving compressed data from the compression section, transmits the compressed data to the display device driver by using a serial data signal. The compression section performs the compression processing with a data compression ratio selected in response to a frame rate with which the display device driver drives the display device. The display device driver receives the serial data signal from the transmission section, generates decompressed data by decompressing the compressed data transmitted by the serial data signal, and drives the display device in response to the decompressed data. The data compression ratio used in the compression processing is set so that the transmission rate of the serial data signal from the transmission section to the display device driver is kept constant independently of the frame rate.
1. An image data processor comprising:
an image compression circuit configured to compress original image data into compressed image data, based on a variable compression ratio;
a data transmission circuit configured to transmit the compressed image data by a data transmission rate; and
a control circuit configured to:
(a) detect a variable frame rate of the original image data;
(b) adjust the variable compression ratio based on the variable frame rate, so that the data transmission rate is kept constant independently of the variable frame rate.
2. The image data processor according to claim 1 ,
wherein the data transmission circuit includes a clock generating circuit,
wherein the clock generating circuit is configured to generate a synchronizing clock signal synchronous with a source clock signal regardless of variation of the variable frame rate.
3. The image data processor according to claim 2 , wherein the clock generating circuit is formed as a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).
4. The image data processor according to claim 1 ,
wherein the compression of the image compression circuit is performed by any one of a plurality of compression methods corresponding the variable compression ratio.