Low quiescent current DC-to-DC converter with increased output voltage accuracy

1. A direct current to direct current (DCDC) converter, comprising:

a hysteresis control circuit comprising a comparator to transmit an enable signal to enable a switching mode;

a switching circuit, operatively coupled to the hysteresis control circuit, to perform a series of switching cycles in the switching mode responsive to receiving the enable signal; and

an error threshold compensation circuit, operatively coupled to the hysteresis control circuit and to the switching circuit, wherein the error threshold compensation circuit is configured to:

detect an output voltage of the DCDC converter subsequent to completion of a subset of the series of switching cycles and prior to completion of the series of switching cycles of the switching mode;

compare the output voltage to a target voltage;

modify a bottom threshold voltage based on a comparison of the output voltage to the target voltage; and

output the bottom threshold voltage to the comparator of the hysteresis control circuit to lower a quiescent current (IQ) of the DCDC converter, wherein the DCDC converter is to enter a power saving mode subsequent to the completion of the series of switching cycles of the switching mode.

2. The DCDC converter of claim 1 , wherein to modify the bottom threshold voltage, the error threshold compensation circuit is configured to:

increase the bottom threshold voltage in response to the output voltage being less than the target voltage based on the comparison; and

decrease the bottom threshold voltage in response to the output voltage being greater than or equal to the target voltage based on the comparison.

3. The DCDC converter of claim 1 , wherein the error threshold compensation circuit is configured to compare the output voltage to the target voltage after at least two consecutive switching cycles are performed in the switching mode of the switching circuit.

4. The DCDC converter of claim 1 , further comprising a filter circuit operatively coupled to the switching circuit, the hysteresis control circuit, and the error threshold compensation circuit, wherein the filter circuit is configured to store energy in the DCDC converter and filter noise from the output voltage.

5. The DCDC converter of claim 1 , wherein the error threshold compensation circuit comprises:

a first comparator, operatively coupled to the switching circuit and the hysteresis control circuit, wherein the first comparator is configured to compare the output voltage to the target voltage to generate a first comparator output during the switching mode of the switching circuit; and

a counter, operatively coupled to the first comparator, the switching circuit, and the hysteresis control circuit, wherein the counter is configured to modify the bottom threshold voltage based on the first comparator output.

6. The DCDC converter of claim 5 , wherein the error threshold compensation circuit further comprises:

a one-shot circuit, operatively coupled to the switching circuit and the counter, wherein the one-shot circuit is configured to enable the counter to receive the first comparator output; and

a trimming circuit, operatively coupled to the counter and the hysteresis control circuit, wherein to modify the bottom threshold voltage, the counter is configured to modify the trimming circuit.

7. The DCDC converter of claim 6 , wherein the error threshold compensation circuit further comprises:

a second comparator, operatively coupled to the switching circuit and the hysteresis control circuit, wherein the second comparator is configured to compare the output voltage to a second threshold voltage to generate a second comparator output voltage; and

a sense logic circuit, operatively coupled to the first comparator and the counter, wherein the sense logic circuit is configured to:

store a plurality of first comparator outputs, wherein each first comparator output of the plurality of first comparator outputs corresponds to a respective switching cycle performed in a current switching mode of the switching circuit;

determine a number of switching cycles performed in the current switching mode of the switching circuit;

select the first comparator output, from the plurality of first comparator outputs, based on the number of switching cycles performed in the current switching mode; and

provide the first comparator output to the counter.

8. The DCDC converter of claim 7 , wherein the error threshold compensation circuit further comprises delay logic, operatively coupled to the sense logic circuit, wherein the delay logic is to delay the operations of the sense logic circuit for a defined duration of time.

9. A system, comprising:

a voltage source; and

a direct current to direct current (DCDC) converter, operatively coupled to the voltage source, comprising:

a hysteresis control circuit comprising a comparator to transmit an enable signal to enable a switching mode;

a switching circuit, operatively coupled to the hysteresis control circuit, to perform a series of switching cycles in the switching mode responsive to receiving the enable signal; and

an error threshold compensation circuit, operatively coupled to the hysteresis control circuit and to the switching circuit, wherein the error threshold compensation circuit is configured to:

detect an output voltage of the DCDC converter subsequent to completion of a subset of the series of switching cycles and prior to completion of the series of switching cycles of the switching mode;

compare the output voltage to a target voltage;

modify a bottom threshold voltage based on a comparison of the output voltage to the target voltage; and

output the bottom threshold voltage to the comparator of the hysteresis control circuit to lower a quiescent current (IQ) of the DCDC converter, wherein the DCDC converter is to enter a power saving mode subsequent to the completion of the series of switching cycles of the switching mode.

10. The system of claim 9 , further comprising a processing device operatively coupled to the DCDC converter.

11. The system of claim 9 , wherein to modify the bottom threshold voltage, the error threshold compensation circuit is configured to:

increase the bottom threshold voltage in response to the output voltage being less than the target voltage based on the comparison; and

decrease the bottom threshold voltage in response to the output voltage being greater than or equal to the target voltage based on the comparison.

12. The system of claim 9 , wherein the error threshold compensation circuit is configured to compare the output voltage to the target voltage after at least two consecutive switching cycles are performed in the switching mode of the switching circuit.

13. The system of claim 9 , wherein the DCDC converter further comprises a filter circuit operatively coupled to the switching circuit, the hysteresis control circuit, and the error threshold compensation circuit, wherein the filter circuit is configured to store energy in the DCDC converter and filter noise from the output voltage.

14. The system of claim 9 , wherein the error threshold compensation circuit comprises:

a first comparator, operatively coupled to the switching circuit and the hysteresis control circuit, wherein the first comparator is configured to compare the output voltage to the target voltage to generate a first comparator output during the switching mode of the switching circuit; and

a counter, operatively coupled to the first comparator, the switching circuit, and the hysteresis control circuit, wherein the counter is configured to modify the bottom threshold voltage based on the first comparator output.

15. The system of claim 14 , wherein the error threshold compensation circuit further comprises:

a one-shot circuit, operatively coupled to the switching circuit and the counter, wherein the one-shot circuit is configured to enable the counter to receive the first comparator output; and

a trimming circuit, operatively coupled to the counter and the hysteresis control circuit, wherein to modify the bottom threshold voltage the counter is configured to modify the trimming circuit.

16. A method, comprising:

responsive to determining that an output voltage of a direct current to direct current (DCDC) converter is below a bottom threshold voltage, transmitting an enable signal to enable a switching mode of the DCDC converter;

initializing a series of switching cycles in the switching mode of the DCDC converter;

comparing the output voltage subsequent to completion of a subset of the series of switching cycles and prior to completion of the series of switching cycles of the switching mode to a target voltage of the DCDC converter;

modifying the bottom threshold voltage based on the comparing of the output voltage to the target voltage;

outputting the bottom threshold voltage to a comparator of a hysteresis control circuit of the DCDC converter to lower a quiescent current (K)) of the DCDC converter; and

entering a power saving mode subsequent to the completion of the series of switching cycles of the switching mode.

17. The method of claim 16 , wherein modifying the bottom threshold voltage comprises:

in response to the output voltage being less that the target voltage, increasing the bottom threshold voltage; and

in response to the output voltage being greater than or equal to the target voltage, decreasing the bottom threshold voltage.

18. The method of claim 16 , further comprising:

determining that at least four switching cycles in the switching mode of the switching mode of the DCDC converter have been performed; and

suspending the switching mode.

19. The method of claim 16 , further comprising:

storing energy in the DCDC converter corresponding to the output voltage; and

filtering noise from the output voltage.

20. The method of claim 16 , wherein modifying the bottom threshold voltage comprises modifying a trimming circuit of the DCDC converter based on the comparing the output voltage to the target voltage.