IP Library Granted Patent US 10,656,993
Granted Patent B2
US 10,656,993 · App. 15/596,939 · Granted May 19, 2020

Apparatus, system, and method to increase data integrity in a redundant storage system

Inventors: Jonathan Thatcher (Liberty Lake, WA); David Flynn (Sandy, UT); Joshua Aune (South Jordan, UT); Jeremy Fillingim (Salt Lake City, UT); Bill Inskeep (West Valley City, UT); John Strasser (Syracuse, UT); Kevin Vigor (Salt Lake City, UT)
Assignee: Unification Technologies LLC
G06F11/1068G06F3/064G06F3/0619G06F3/0688G06F11/073G06F11/108G06F11/1008G06F11/1092G11C29/52H03M13/05H03M13/6502G06F11/0766H03M13/13
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Quick Facts
Patent No.
US 10,656,993
App. No.
15/596,939
Granted
May 19, 2020
Kind
B2
Abstract

In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data.

Claims (40)

1. A system comprising:

a computer apparatus comprising processing circuitry to request and receive data; and

a storage device connected to the computer apparatus via an interface, the storage device comprising a storage controller and one or more storage elements;

the computer apparatus configured to send a read request to the storage device to read data;

the storage device configured to receive the read request from the computer apparatus via the interface, and in response, read data from an error correcting code (ECC) chunk stored in an array of an N+P number of storage elements, wherein the N number of storage elements each store a portion of the ECC chunk and the P number of storage elements store parity data for the ECC chunk stored on the N storage elements;

the storage device further configured to correct errors in the data read from the ECC chunk using Error Correcting Code (“ECC”) when the number of errors are correctable using the ECC, and to

correct errors in the data read from the ECC chunk with substitute data from a substitute storage element of the N+P number of storage elements when the number of errors are uncorrectable using the ECC;

the storage device configured to return the requested data to the computer apparatus via the interface; and

the computer apparatus configured to receive the data requested from the storage device.

2. The system of claim 1 , wherein the data from the ECC chunk is read from an X number of storage elements of the N+P number of storage elements, where (N+P)>X≥N.

3. The system of claim 1 , wherein when a portion of the data read from the ECC chunk comprises parity data, the storage device is configured to regenerate a missing portion of the ECC chunk using the parity data.

4. The system of claim 3 , wherein, when the data read from the ECC chunk and the regenerated portion of the ECC chunk comprises errors above a correctable bit threshold, the storage device is configured to replace the regenerated portion of the ECC chunk with the substitute data, wherein the substitute data and the data read from the ECC chunk together comprise a substitute ECC chunk having a number of bit errors below the correctable bit error threshold.

5. The system of claim 3 , wherein the parity data is combined with the substitute data to produce generated substitute data, wherein the generated substitute data and the data read from the ECC chunk together comprise a substitute ECC chunk having a number of bit errors below a correctable bit error threshold.

6. The system of claim 1 , wherein a missing portion of the ECC chunk is generated by way of a parity computation comprising the data read from the ECC chunk and parity data from the substitute storage element, wherein the generated missing portion and the data read from the ECC chunk together comprise a substitute ECC chunk having a number of bit errors below a correctable bit error threshold.

7. The system of claim 1 , wherein the storage device comprises ECC check circuitry configured to determine whether the number of errors are correctable using the ECC.

8. The system of claim 1 , wherein a substitute ECC chunk is generated from the data read from the ECC chunk and the substitute data.

9. The system of claim 8 , wherein the substitute ECC chunk comprises one of no errors and a number of errors that are correctable using ECC.

10. The system of claim 1 , wherein the storage device is configured to rotate from which storage elements the data is read.

11. The system of claim 2 , wherein the X storage elements do not store parity data for the ECC chunk.

12. The system of claim 1 , wherein the P number of storage elements include a data mirror.

13. The system of claim 1 , wherein the computer apparatus comprises one of:

a computer device connected to the storage device within an enclosure housing;

a server device sending storage requests to the storage device; or

a client device in communicate on with and sending read requests to the storage device.

14. An apparatus comprising:

processing circuitry;

a storage device comprising a storage controller and one or more storage elements; and

an interface connecting the storage device to the processing circuitry for reading data from the storage device;

the processing circuitry configured to send a read request to the storage device to read data;

the storage device configured to receive the read request via the interface, and in response, read data from an error correcting code (ECC) chunk stored in an array of an N+P number of storage elements, wherein the N number of storage elements each store a portion of the ECC chunk and the P number storage elements store parity data for the N storage elements;

the storage device configured to correct the data read from the ECC chunk using Error Correcting Code (“ECC”) when the number of errors are correctable using the ECC, and

correct the data read from the ECC chunk with substitute data from a substitute storage element of the N+P number of storage elements when the number of errors are uncorrectable using the ECC; and

the storage device configured to return the requested data to the computer apparatus via the interface; and

the processing circuitry configured to receive the data requested from the storage device.

15. The apparatus of claim 14 , wherein the data read from the ECC chunk is read from an X number of storage elements of the N+P number of storage elements, where (N+P)>X≥N.

16. The apparatus of claim 14 , wherein when a portion of the data read from the ECC chunk comprises parity data, the storage device is configured to regenerate a missing portion of the ECC chunk using the parity data.

17. The apparatus of claim 14 , wherein a missing portion of the ECC chunk is generated by way of a parity computation comprising the data read from the ECC chunk and parity data from the substitute storage element, and wherein the generated missing portion and data read from the ECC chunk together comprise a substitute ECC chunk having a number of bit errors below the correctable bit error threshold.

18. The apparatus of claim 14 , wherein the storage device comprises ECC check circuitry configured to determine whether the number of errors are correctable using the ECC.

19. The apparatus of claim 14 , wherein a substitute ECC chunk is generated from the data read from the ECC chunk and the substitute data.

20. The apparatus of claim 14 , wherein the storage device is configured to rotate from which storage elements of the array the data from the ECC chunk is read.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 052853 FRAME: 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 15, 2021
From: UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 058223/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 15, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
To: UNIFICATION TECHNOLOGIES LLC
Reel/Frame 058134/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2020
From: ACACIA RESEARCH GROUP LLC
To: UNIFICATION TECHNOLOGIES LLC
Reel/Frame 052096/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 5, 2020
From: FIO SEMICONDUCTOR TECHNOLOGIES, LLC
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 052095/0903 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT DOCUMENT FILED PREVIOUSLY RECORDED ON REEL 047702 FRAME 0413. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 16, 2019
From: LONGITUDE ENTERPRISE FLASH S.A.R.I.
To: FIO SEMICONDUCTOR TECHNOLOGIES, LLC
Reel/Frame 048918/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2018
From: LONGITUDE ENTERPRISE FLASH S.A.R.I.
To: FIO SEMICONDUCTOR TECHNOLOGIES LIMITED
Reel/Frame 047702/0413 →
Cited By (4)
US 12,273,388 US 12,355,820 US 12,387,270 US 12,519,818