Method and device for TIA overload control in low power applications

1. A transimpedance amplifier (TIA) device comprising:

a semiconductor substrate;

a TIA configured on the semiconductor substrate, the TIA comprising an input terminal and an output terminal; and

an overload buffer module coupled to the input terminal of the TIA, the overload buffer module comprising:

a variable current source having an input and an output, and

a biased buffer diode coupled to the output of the variable current source;

wherein the biased buffer diode is coupled to a ground node; and

wherein the variable current source is configured as a control source to replicate a DC signal at the output.

2. The device of claim 1 wherein the variable current source is configured from a P-type MOSFET transistor.

3. A transimpedance amplifier (TIA) device comprising:

a semiconductor substrate;

a TIA configured on the semiconductor substrate, the TIA comprising an input terminal and an output terminal; and

an overload buffer module coupled to the input terminal of the TIA, the overload buffer module comprising:

a variable current source having an input and an output, and

a biased buffer diode coupled to the output of the variable current source;

wherein the biased buffer diode is coupled to a ground node; and

wherein the variable current source is configured as a feed-forward source from gain control.

4. The device of claim 1 wherein the biased buffer diode is configured as a down-biased diode.

5. The device of claim 1 wherein the biased buffer diode is configured as an AC sink.

6. A method for operating a transimpedance amplifier (TIA) device:

providing a transimpedance amplifier (TIA) device comprising:

a semiconductor substrate;

a TIA configured on the semiconductor substrate, the TIA comprising an input terminal and an output terminal; and

an overload buffer module coupled to the input terminal of the TIA, the overload buffer module comprising

a variable current source having an input and an output, and

a biased buffer diode coupled to the output of the variable current source;

wherein the biased buffer diode is coupled to a ground node;

sending a DC input signal to the input of the TIA;

replicating, by the overload buffer module, the current-voltage (I/V) characteristics of the DC input signal at the output of the overload buffer module, wherein the overload buffer module reduces a total harmonic distortion (THD) of a DC output signal from the output of the TIA;

wherein the variable current source is configured as a control source to replicate a DC signal at the output.

7. The method of claim 6 wherein the variable current source is configured from a P-type MOSFET transistor.

8. A method for operating a transimpedance amplifier (TIA) device:

providing a transimpedance amplifier (TIA) device comprising:

a semiconductor substrate;

a TIA configured on the semiconductor substrate, the TIA comprising an input terminal and an output terminal; and

an overload buffer module coupled to the input terminal of the TIA, the overload buffer module comprising

a variable current source having an input and an output, and

a biased buffer diode coupled to the output of the variable current source;

wherein the biased buffer diode is coupled to a ground node;

sending a DC input signal to the input of the TIA;

replicating, by the overload buffer module, the current-voltage (I/V) characteristics of the DC input signal at the output of the overload buffer module, wherein the overload buffer module reduces a total harmonic distortion (THD) of a DC output signal from the output of the TIA; and

wherein the variable current source is configured as a feed-forward source from gain control.

9. The method of claim 6 wherein the biased buffer diode is configured as a down-biased diode.

10. A transimpedance amplifier (TIA) device comprising:

a semiconductor substrate comprising a plurality of CMOS cells, each of the CMOS cells comprising a deep n-type well region;

a first TIA comprising a first input terminal and a first output terminal, the first TIA configured using a plurality of first CMOS cells;

a first overload buffer module coupled to the first input terminal of the first TIA, the first overload buffer module comprising:

a first variable current source having an input and an output, and

a first biased buffer diode coupled to the output of the variable current source;

wherein the first biased buffer diode is coupled to a ground node;

a second TIA comprising a second input terminal and a second output terminal, the second TIA configured using a plurality of second CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells;

a second overload buffer module coupled to the second input terminal of the second TIA, the second overload buffer module comprising:

a second variable current source having an input and an output, and

a second biased buffer diode coupled to the output of the second variable current source;

wherein the second biased buffer diode is coupled to the ground node;

a photodiode coupled between the first input terminal and the second input terminal; and

a Level Shifting/Differential Amplifier (LS/DA) coupled to the first output terminal and the second output terminal.

11. The device of claim 10 wherein the first and second variable current sources are configured from P-type MOSFET transistors; and

wherein the first and second variable current sources are configured as a control sources to replicate a DC signal at each of the outputs for the first and second variable current sources or as a feed-forward sources from gain controls.

12. The device of claim 10 wherein the first and second biased buffer diode are configured as down-biased diodes.

13. The device of claim 10 wherein the first TIA comprises a VDDL level and a VSSL level; and wherein the second TIA comprises a VDDH level and a VSSH level.

14. The device of claim 10 wherein the plurality of CMOS cells is configured using a 28 nm process technology; and

wherein the photodiode is characterized by a responsivity value ranging from about 0.6 to about 0.9 Amps/Watt.

15. The device of claim 10 wherein each of the first TIA and the second TIA is provided with a supply voltage independent of a photodiode differential voltage provided on the first input terminal and the second input terminal; and

wherein each of the first TIA and the second TIA includes a first switch device configured for at least two bit rates.

16. The device of claim 10 wherein the LS/DA comprises an up-shifting device and a down-shifting device configured to mitigate any mismatch in data bits between the first TIA and the second TIA; wherein the LS/DA comprises a differential amplifier having a differential voltage output.

17. The device of claim 10 wherein the LS/DA comprises an up-shifting device and a down-shifting device configured to mitigate any mismatch in data bits between the first TIA and the second TIA; and

further comprising a gain amplifier configured to correct any losses provided by either the up-shifting device or the down-shifting device; wherein the LS/DA comprises a differential amplifier having a differential voltage output.

18. The device of claim 10 further comprising:

an AC source coupled to a first capacitor and configured to the first output terminal, the AC source also coupled to a second capacitor and configured to the second output terminal; and

a level shifter configured with the LS/DA.