METHOD FOR MANUFACTURING A TRANSISTOR HAVING A SHARP JUNCTION BY FORMING RAISED SOURCE-DRAIN REGIONS BEFORE FORMING GATE REGIONS AND CORRESPONDING TRANSISTOR PRODUCED BY SAID METHOD
A transistor is fabricated by growing an epitaxial layer of semiconductor material on a semiconductor layer and forming an opening extending through the epitaxial layer at the gate location. This opening provides, from the epitaxial layer, a source epitaxial region on one side of the opening and a drain epitaxial region on an opposite side of the opening. The source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region are annealed into a single crystal transistor source region. Additionally, the drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region are annealed into a single crystal transistor drain region. A third portion of the semiconductor layer between the transistor source and drain regions forms a transistor channel region. A transistor gate electrode is then formed in the opening above the transistor channel region.
1 . An integrated circuit transistor, comprising:
a semiconductor layer including an active region;
an epitaxial layer of semiconductor material on said semiconductor layer and including an opening extending through said epitaxial layer of semiconductor material to provide, from said epitaxial layer of semiconductor material, a source epitaxial region on one side of said opening and a drain epitaxial region on an opposite side of said opening;
a transistor source region comprising a combination of said source epitaxial region and a first portion of the semiconductor layer underlying the source epitaxial region together as a single crystal region;
a transistor drain region comprising a combination of said drain epitaxial region and a second portion of the semiconductor layer underlying the drain epitaxial region together as a single crystal region;
wherein a third portion of the semiconductor layer between transistor source and drain regions forms a transistor channel region; and
a transistor gate electrode in said opening above the transistor channel region.
2 . The integrated circuit transistor of claim 1 , further comprising trench isolations that delimit the active region.
3 . The integrated circuit transistor of claim 1 , wherein the semiconductor layer is an upper layer of a silicon on insulator (SOI) substrate.
4 . The integrated circuit transistor of claim 1 , wherein the semiconductor layer separated by a cavity from a lower semiconductor layer.
5 . The integrated circuit transistor of claim 4 , wherein the single crystal regions for the transistor source and drain regions, respectively, extend completely through a thickness of the semiconductor layer to reach said cavity.
6 . The integrated circuit transistor of claim 4 , wherein said lower semiconductor layer comprises a first portion of a stress released semiconductor layer.
7 . The integrated circuit transistor of claim 4 , wherein the lower semiconductor layer is positioned within including a recessed portion of a stress released semiconductor layer.
8 . The integrated circuit transistor of claim 4 , wherein the semiconductor layer and lower semiconductor layer are made of a same semiconductor material.
9 . The integrated circuit transistor of claim 8 , wherein the epitaxial layer is made of said same semiconductor material.
10 . The integrated circuit transistor of claim 9 , wherein the semiconductor material is selected from the group consisting of a silicon-germanium material and an indium-gallium-arsenic material.
11 . The integrated circuit transistor of claim 1 , wherein the transistor gate electrode comprises:
a dielectric layer in the opening;
a metal liner on the dielectric layer; and
a metal material filling said opening.
12 . The integrated circuit transistor of claim 11 , wherein the metal liner and metal material are insulated from a portion of the transistor source region and a portion of the transistor drain region solely by the dielectric layer in the opening.
13 . The integrated circuit transistor of claim 1 , further comprising sidewall spacers on side walls of said opening.
14 . The integrated circuit transistor of claim 13 , wherein a bottom-most surface of the sidewall spacers is in contact with a top-most surface of the transistor source region and transistor drain region.
15 . The integrated circuit transistor of claim 13 , wherein a bottom-most surface of the sidewall spacers is in contact with an intermediate surface of the transistor source region and transistor drain region.
16 . The integrated circuit transistor of claim 15 , wherein the transistor gate electrode comprises:
a dielectric layer in the opening;
a metal liner on the dielectric layer; and
a metal material filling said opening; and
wherein the metal liner and metal material are insulated the transistor source region and the transistor drain region at the intermediate surface solely by the dielectric layer in the opening.
17 . The integrated circuit transistor of claim 1 , further comprising:
a dielectric layer over the epitaxial layer of semiconductor material;
a first opening in said dielectric layer; and
sidewall spacers on side walls of said first opening to define a second opening that is aligned with said opening.
18 . The integrated circuit transistor of claim 1 , wherein the single crystal regions for the transistor source and drain regions, respectively, are formed by annealed source and drain epitaxial regions and underlying portions of the semiconductor layer.
19 . The integrated circuit transistor of claim 1 , wherein the integrated circuit transistor is a p-channel device.
20 . The integrated circuit transistor of claim 1 , wherein the integrated circuit transistor is an n-channel device.
21 . An integrated circuit transistor, comprising:
an upper semiconductor layer separated by a cavity from a lower semiconductor layer;
an epitaxial layer on said upper semiconductor layer and including an opening extending through said epitaxial layer to provide, from said epitaxial layer, a source epitaxial region on one side of said opening and a drain epitaxial region on an opposite side of said opening;
a transistor source region comprising a combination of said source epitaxial region and a first portion of the upper semiconductor layer underlying the source epitaxial region together as a single crystal region that extends to said cavity;
a transistor drain region comprising a combination of said drain epitaxial region and a second portion of the upper semiconductor layer underlying the drain epitaxial region together as a single crystal region that extends to said cavity;
wherein a third portion of the upper semiconductor layer between transistor source and drain regions forms a transistor channel region; and
a transistor gate electrode in said opening above the transistor channel region.
22 . An integrated circuit transistor, comprising:
a semiconductor layer including an active region;
an epitaxial layer of semiconductor material on said semiconductor layer;
a dielectric layer on said epitaxial layer;
an opening extending through said dielectric layer and said epitaxial layer of semiconductor material to provide:
a transistor source region formed from a combination of a source epitaxial region on one side of said opening and a first portion of the semiconductor layer underlying the source epitaxial region together as a single crystal region; and
a transistor drain region formed from a combination of a drain epitaxial region on opposite side of said opening and a second portion of the semiconductor layer underlying the drain epitaxial region together as a single crystal region;
wherein a third portion of the semiconductor layer between transistor source and drain regions forms a transistor channel region;
sidewall spacers on side walls of said opening adjacent the dielectric layer wherein a bottom-most surface of said sidewall spacers is in contact with a top surface of the transistor source and drain regions;
a transistor gate electrode in said opening; and
a dielectric layer in said opening and insulating the transistor gate electrode from the transistor source and drain regions.
23 . The integrated circuit transistor of claim 22 , wherein the semiconductor layer separated by a cavity from a lower semiconductor layer.
24 . The integrated circuit transistor of claim 23 , wherein the single crystal regions for the transistor source and drain regions, respectively, extend completely through a thickness of the semiconductor layer to reach said cavity.
25 . An integrated circuit transistor, comprising:
a semiconductor layer including an active region;
an epitaxial layer of semiconductor material on said semiconductor layer and including an opening extending through said epitaxial layer of semiconductor material to provide:
a transistor source region formed from a combination of a source epitaxial region on one side of said opening and a first portion of the semiconductor layer underlying the source epitaxial region together as a single crystal region; and
a transistor drain region formed from a combination of a drain epitaxial region on opposite side of said opening and a second portion of the semiconductor layer underlying the drain epitaxial region together as a single crystal region;
wherein a third portion of the semiconductor layer between transistor source and drain regions forms a transistor channel region;
sidewall spacers on side walls of said opening;
a transistor gate electrode in said opening and insulated in a lateral direction from the transistor source and drain regions by at least the sidewall spacers; and
a dielectric layer at a bottom of said opening, said transistor gate electrode insulated in a vertical direction from the transistor source and drain regions and the transistor channel region solely by said dielectric layer at the bottom of said opening, said vertical direction being perpendicular to the lateral direction.
26 . The integrated circuit transistor of claim 25 , wherein the semiconductor layer separated by a cavity from a lower semiconductor layer.
27 . The integrated circuit transistor of claim 26 , wherein the single crystal regions for the transistor source and drain regions, respectively, extend completely through a thickness of the semiconductor layer to reach said cavity.