Method of manufacturing semiconductor integrated circuit device
View Patent ↗Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
1. A method of manufacturing a semiconductor integrated circuit device, comprising:
an N-type well layer formation step of forming a silicon oxide film and a silicon nitride film on an N-type semiconductor substrate, forming an opening through the silicon nitride film present on a region for forming an N-type well layer so as to form a silicon nitride film opening portion, and implanting an N-type impurity comprising phosphorous by an ion implantation;
a P-type well layer formation step of forming a silicon oxide film on the silicon nitride film opening portion and implanting a P-type impurity comprising one of boron and BF 2 into a region other than the region for forming the N-type well layer, from which the silicon nitride film is removed, by the ion implantation in a self-aligned manner;
a third N-type low-concentration impurity layer formation step of implanting an N-type impurity comprising arsenic into a region for forming a third N-type low-concentration impurity layer, by the ion implantation;
a well diffusion step of simultaneously forming the N-type well layer, a P-type well layer, and the third N-type low-concentration impurity layer by a thermal treatment;
a second N-type low-concentration impurity layer formation step of forming a silicon oxide film and a silicon nitride film, forming an opening through the silicon nitride film present on a region for forming a second N-type low-concentration impurity region of a high withstanding-voltage NMOS transistor, and implanting an N-type impurity comprising phosphorous by the ion implantation;
a step of forming a silicon oxide film on the region for forming the second N-type low-concentration impurity layer in the silicon nitride film opening portion, to thereby form an insulating film for electric field relaxation between a gate and a drain of the high withstanding-voltage NMOS transistor;
a gate insulating film formation step of forming a gate insulating film of a low withstanding-voltage NMOS transistor, a low withstanding-voltage PMOS transistor, and the high withstanding-voltage NMOS transistor;
a gate electrode formation step of forming a gate electrode on the gate insulating film;
a first N-type low-concentration impurity layer formation step of implanting phosphorus into a region for forming a drain of the low withstanding-voltage NMOS transistor and a region for forming a source of the low withstanding-voltage NMOS transistor;
a P-type low-concentration impurity layer formation step of implanting one of boron and BF 2 into a region for forming a drain of the low withstanding-voltage PMOS transistor and a region for forming a source of the low withstanding-voltage PMOS transistor; and
a high-concentration drain/source layer formation step of forming an N-type low-concentration impurity layer containing arsenic in each of the region for forming the drain and the region for forming the source of the low withstanding-voltage NMOS transistor and the region for forming the drain and the region for forming the source of the high withstanding-voltage NMOS transistor, and forming a P-type impurity layer containing BF 2 in the region for forming the drain of the low withstanding-voltage PMOS transistor and the region for forming the source of the low withstanding-voltage PMOS transistor.
2. A method of manufacturing a semiconductor integrated circuit device, comprising:
an N-type well layer formation step of forming a silicon oxide film and a silicon nitride film on an N-type semiconductor substrate, forming an opening through the silicon nitride film present on a region for forming an N-type well layer so as to form a silicon nitride film opening portion, and implanting an N-type impurity comprising phosphorous by an ion implantation;
a first P-type well layer formation step of forming a silicon oxide film on the silicon nitride film opening portion and implanting a P-type impurity comprising one of boron and BF 2 into a region other than the region for forming the N-type well layer, from which the silicon nitride film is removed, by the ion implantation in a self-aligned manner;
a third N-type low-concentration impurity layer formation step of peeling off the silicon nitride film, forming another silicon nitride film, forming an opening through the silicon nitride film present on a region for forming a third N-type low-concentration impurity layer, implanting an N-type impurity comprising arsenic by the ion implantation;
a second P-type well layer formation step of forming a silicon oxide film on the silicon nitride film opening portion, and implanting a P-type impurity comprising one of boron and BF 2 into a region other than the region for forming the third N-type low-concentration impurity layer and the region for forming the N-type well layer on the N-type semiconductor substrate, from which the silicon nitride film is removed, by the ion implantation in a self-aligned manner;
a well diffusion step of simultaneously forming an N-type well layer, a first P-type well layer, a second P-type well layer, and the third N-type low-concentration impurity layer by a thermal treatment;
a second N-type low-concentration impurity layer formation step of forming a silicon oxide film and a silicon nitride film, forming an opening through the silicon nitride film present on a region for forming a second N-type low-concentration impurity region of a high withstanding-voltage NMOS transistor, and implanting an N-type impurity comprising phosphorous by the ion implantation;
a step of forming a silicon oxide film on the region for forming the second N-type low-concentration impurity layer in the silicon nitride film opening portion, to thereby form an insulating film for electric field relaxation between a gate and a drain of the high withstanding-voltage NMOS transistor;
a gate insulating film formation step of forming a gate insulating film of a low withstanding-voltage NMOS transistor, a low withstanding-voltage PMOS transistor, and the high withstanding-voltage NMOS transistor;
a gate electrode formation step of forming a gate electrode on the gate insulating film;
a first N-type low-concentration impurity layer formation step of implanting phosphorus into a region for forming a drain of the low withstanding-voltage NMOS transistor and a region for forming a source of the low withstanding-voltage NMOS transistor;
a P-type low-concentration impurity layer formation step of implanting one of boron and BF 2 into a region for forming a drain of the low withstanding-voltage PMOS transistor and a region for forming a source of the low withstanding-voltage PMOS transistor; and
a high-concentration drain/source layer formation step of forming an N-type low-concentration impurity layer containing arsenic in each of the region for forming the drain and the region for forming the source of the low withstanding-voltage NMOS transistor and the region for forming the drain and the region for forming the source of the high withstanding-voltage NMOS transistor, and forming a P-type impurity layer containing BF 2 in the region for forming the drain of the low withstanding-voltage PMOS transistor and the region for forming the source of the low withstanding-voltage PMOS transistor.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 2 , wherein:
an impurity dose amount in the N-type well layer formation step is from 3×10 12 /cm 2 to 3×10 13 /cm 2 ;
an impurity dose amount in the first P-type well layer formation step is from 2×10 12 /cm 2 to 2×10 13 /cm 2 ;
an impurity dose amount in the second P-type well layer formation step is from 5×10 12 /cm 2 to 2×10 13 /cm 2 ;
an impurity dose amount in the third N-type low-concentration impurity layer formation step is from 8×10 12 /cm 2 to 7×10 13 /cm 2 ;
an impurity dose amount in the second N-type low-concentration impurity layer formation step is from 1×10 12 /cm 2 to 7×10 13 /cm 2 ;
an impurity dose amount in the first N-type low-concentration impurity layer formation step is from 2×10 12 /cm 2 to 2×10 14 /cm 2 ;
an impurity dose amount in the P-type low-concentration impurity layer formation step is from 2×10 12 /cm 2 to 2×10 14 /cm 2 ; and
a dose amount of the N-type impurity and a dose amount of the P-type impurity in the high-concentration drain/source layer formation step are 2×10 15 /cm 2 or larger.