Process for forming a layer of equiaxed titanium nitride and a MOSFET device having a metal gate electrode including a layer of equiaxed titanium nitride
Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
1. An integrated circuit, comprising:
a substrate;
a gate oxide layer deposited over the substrate;
a work function metal nitride layer deposited over the gate oxide layer;
a gate electrode layer deposited over the work function metal nitride layer;
wherein the work function metal nitride layer is made of equiaxed grains.
2. The integrated circuit of claim 1 , wherein the gate oxide layer is made of a high-k dielectric material.
3. The integrated circuit of claim 1 , wherein the work function metal nitride layer is made of a titanium nitride material.
4. The integrated circuit of claim 1 , wherein the work function metal nitride layer is deposited by physical vapor deposition in radio frequency mode (RF-PVD).
5. The integrated circuit of claim 1 , wherein the gate oxide layer includes nitrogen provided to adjust centering of a transistor device having a transistor gate formed from the work function metal nitride layer and gate electrode layer.
6. The integrated circuit of claim 1 , wherein the gate electrode layer is made of a polysilicon material.
7. An integrated circuit, comprising:
a substrate;
a gate oxide layer deposited over the substrate;
a work function metal nitride layer deposited over the gate oxide layer;
a gate electrode layer deposited over the work function metal nitride layer;
wherein the work function metal nitride layer has an equiaxed micromorphology.
8. The integrated circuit of claim 7 , wherein the gate oxide layer is made of a high-k dielectric material.
9. The integrated circuit of claim 7 , wherein the work function metal nitride layer is made of a titanium nitride material.
10. The integrated circuit of claim 7 , wherein the work function metal nitride layer is deposited by physical vapor deposition in radio frequency mode (RF-PVD).
11. The integrated circuit of claim 7 , wherein the gate oxide layer includes nitrogen provided to adjust centering of a transistor device having a transistor gate formed from the work function metal nitride layer and gate electrode layer.
12. The integrated circuit of claim 7 , wherein the gate electrode layer is made of a polysilicon material.
13. An integrated circuit, comprising:
a substrate;
a gate oxide layer deposited over the substrate;
a work function metal nitride layer deposited over the gate oxide layer;
a gate electrode layer deposited over the work function metal nitride layer;
wherein the work function metal nitride layer is made of an electrically and mechanically isotropic material.
14. The integrated circuit of claim 13 , wherein the electrically and mechanically isotropic material comprises at least two rows of grains in a vertical direction above the gate oxide layer, wherein the grains with each row do not have a preferred direction.
15. The integrated circuit of claim 13 , wherein the electrically and mechanically isotropic material comprises equiaxed grains.
16. The integrated circuit of claim 13 , wherein the gate oxide layer is made of a high-k dielectric material.
17. The integrated circuit of claim 13 , wherein the work function metal nitride layer is made of a titanium nitride material.
18. The integrated circuit of claim 13 , wherein the work function metal nitride layer is deposited by physical vapor deposition in radio frequency mode (RF-PVD).
19. The integrated circuit of claim 13 , wherein the gate oxide layer includes nitrogen provided to adjust centering of a transistor device having a transistor gate formed from the work function metal nitride layer and gate electrode layer.
20. The integrated circuit of claim 13 , wherein the gate electrode layer is made of a polysilicon material.