Track and hold amplifiers
View Patent ↗An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.
1. A device, comprising:
an emitter follower transistor coupled to each of an input and an output;
a charging node coupled between the output and a voltage supply, the charging node further coupled between a collector and an emitter of the emitter follower transistor; and
a cascode switch including a first path coupled to the input and a second path coupled to the output, wherein each of the first and second paths includes a bipolar transistor and a field-effect transistor (FET), and wherein the first path and the second path are substantially symmetrical and respectively electrically passively couple the input and the output to a common node, the cascode switch configured to:
cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode; and
cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode.
2. The device of claim 1 , the cascode switch comprising:
a first bipolar transistor coupled to the input;
a second bipolar transistor coupled to the output and the first bipolar transistor;
a first field-effect transistor (FET) coupled to the first bipolar transistor and configured to receive a hold signal during the hold mode; and
a second FET coupled to the second bipolar transistor and configured to receive a track signal during the track mode.
3. The device of claim 2 , wherein a gate of the first FET is configured to receive a track signal to cause the first FET to operate in a conductive state during the track mode.
4. The device of claim 2 , wherein a gate of the second FET is configured to receive a hold signal to cause the second FET to operate in a conductive state during the hold mode.
5. The device of claim 1 , further comprising an input buffer coupled to the input.
6. The device of claim 1 , further comprising:
a second emitter follower transistor coupled to each of the input and the output;
a second charging node coupled to the output, the charging node further coupled to the input via the second emitter follower transistor; and
a second cascode switch coupled to each of the input and the output and configured to:
cause the second emitter follower transistor to operate in a conductive state and charge the second charging node during the track mode; and
cause the second emitter follower transistor to operate in a non-conductive state to isolate the second charging node from the input during the hold mode.
7. The device of claim 1 , further comprising at least one feedforward capacitor coupled to the output.
8. The device of claim 1 , wherein the cascode switch comprises a metal-oxide-semiconductor-heterojunction bipolar transistor (MOS-HBT) cascode switch.
9. An optical receiver, comprising:
an analog-to-digital converter (ADC); and
a track and hold amplifier (THA) coupled to the ADC and including:
an emitter follower transistor coupled to each of an input of the THA and an output of the THA;
a charging node coupled between the output and a voltage supply, the charging node further coupled between a collector and an emitter of the emitter follower transistor; and
a cascode switch including a first path coupled to the input and a second path coupled to the output, wherein each of the first and second paths includes a bipolar transistor and a field-effect transistor (FET), and wherein the first path and the second path are substantially symmetrical and respectively electrically passively couple the input and the output to a common node, the cascode switch configured to:
cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode; and
cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode.
10. The optical receiver of claim 9 , the cascode switch comprising:
a first bipolar transistor coupled to the input;
a second bipolar transistor coupled to the output and the first bipolar transistor;
a first field-effect transistor (FET) coupled to the first bipolar transistor and configured to receive a hold signal during the hold mode; and
a second FET coupled to the second bipolar transistor and configured to receive a track signal during the track mode.
11. The optical receiver of claim 10 , wherein a gate of the first FET is configured to receive a track signal to cause the first FET to operate in a conductive state during the track mode.
12. The optical receiver of claim 10 , wherein a gate of the second FET is configured to receive a hold signal to cause the second FET to operate in a conductive state during the hold mode.
13. The optical receiver of claim 9 , further comprising an input buffer coupled to the input of the THA.
14. The optical receiver of claim 9 , further comprising:
a second emitter follower transistor coupled to each of the input and the output;
a second charging node coupled to the output, the second charging node further coupled to the input via the second emitter follower; and
a second cascode switch coupled to each of the input and the output and configured to:
cause the second emitter follower transistor to operate in a conductive state and charge the second charging node during the track mode; and
cause the second emitter follower transistor to operate in a non-conductive state to isolate the second charging node from the input during the hold mode.
15. The optical receiver of claim 9 , further comprising at least one feedforward capacitor coupled to the output of the THA.
16. A device, comprising:
a plurality of emitter follower transistors, each emitter follower transistor of the plurality of emitter follower transistors coupled to each of an input and an output;
a plurality of charging nodes coupled to the output, each charging node of the plurality of charging nodes further coupled between a collector and an emitter of at least one emitter follower transistor of the plurality of emitter follower transistors; and
a plurality of cascode switches, each cascode switch of the plurality of cascode switches including a first path coupled to the input and a second path coupled to the output, wherein each of the first and second paths includes a bipolar transistor and a field-effect transistor (FET), and wherein the first path and the second path are substantially symmetrical and respectively electrically passively couple the input and the output to a common node, each cascode switch configured to:
cause an emitter follower transistor of the plurality of emitter follower transistors to operate in a conductive state and charge a charging node of the plurality of charging nodes during a track mode; and
cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode.
17. The device of claim 16 , further comprising an input buffer coupled to the input.
18. The device of claim 16 , wherein each cascode switch of the plurality of cascode switches comprises:
a first bipolar transistor coupled to the input;
a second bipolar transistor coupled to the output and the first bipolar transistor;
a first field-effect transistor (FET) coupled to the first bipolar transistor and configured to receive a hold signal during the hold mode; and
a second FET coupled to the second bipolar transistor and configured to receive a track signal during the track mode.
19. A method, comprising:
receiving an input signal at an input coupled to an emitter follower transistor including a charging node coupled between a collector and an emitter of the emitter follower transistor;
configuring a cascode switch to have a first path coupled to the input and a second path coupled to an output, wherein each of the first and second paths includes a bipolar transistor and a field-effect transistor (FET), and wherein the first path and the second path are substantially symmetrical, and electrically passively coupling the input and the output to a common node to cause the emitter follower transistor to operate in a conductive state to couple the input to each of a charging node and the output during a track mode; and
configuring the cascode switch to cause the emitter follower transistor to operate in a non-conductive state to isolate the input from each of the charging node and the output during a hold mode.
20. The method of claim 19 , wherein receiving an input signal comprises receiving the input signal from an input buffer.