Efficient readout from memory cells using data compression
A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed. The output storage values and the compressed confidence levels are transferred from the memory cells over an interface to a memory controller.
1. An apparatus, comprising:
a memory controller;
a plurality of memory cells; and
a circuit configured to:
read a plurality of values from a subset of the plurality of memory cells using a threshold value, wherein a particular value of the plurality of values is indicative of data stored in a particular memory cell of the subset of the plurality of memory cells;
determine a plurality of multi-bit confidence levels using the plurality of values, wherein a particular multi-bit confidence level of the plurality of multi-bit confidence levels is indicative of a difference between a particular value and the threshold value; and
transfer the plurality of multi-bit confidence levels to the memory controller,
wherein the memory controller is configured to reconstruct the data stored in the particular memory cell of the subset of the plurality of memory cells using the multi-bit confidence levels.
2. The apparatus of claim 1 , wherein to transfer the plurality of multi-bit confidence levels to the memory controller, the circuit is further configured to generate a plurality of compressed confidence levels using the plurality of multi-bit confidence levels.
3. The apparatus of claim 2 , wherein to generate the plurality of compressed confidence levels, the circuit is further configured to run-length encode the plurality of multi-bit confidence levels.
4. The apparatus of claim 2 , wherein to generate the plurality of compressed confidence levels, the circuit is further configured to combine each confidence level of the plurality of multi-bit confidence levels using a logical-AND operation to generate an indicator value.
5. The apparatus of claim 4 , wherein the circuit is coupled to the memory controller via a data bus, and wherein the circuit is further configured to send the indicator value to the memory controller using at least one wire separate from the data bus.
6. The apparatus of claim 1 , wherein each memory cell of the plurality of memory cells includes a non-volatile memory cell.
7. A method, comprising:
reading, by a circuit, a plurality of values from a subset of a plurality of memory cells using a threshold value, wherein a particular value of the plurality of values is indicative of data stored in a particular memory cell of the subset of the plurality of memory cells;
determining, by the circuit, a plurality of multi-bit confidence levels using the plurality of values, wherein a particular multi-bit confidence level of the plurality of multi-bit confidence levels is indicative of a difference between a particular value and the threshold value;
transferring, by the circuit, the plurality of multi-bit confidence levels to a controller; and
reconstructing, by the controller, the data stored in the particular memory cell of the subset of the plurality of memory cells using the plurality of multi-bit confidence levels.
8. The method of claim 7 , wherein transferring, by the circuit, the plurality of multi-bit confidence levels to the controller includes generating, by the circuit, a plurality of compressed confidence levels using the plurality of multi-bit confidence levels.
9. The method of claim 8 , wherein generating the plurality of compressed confidence levels includes run-length encoding the plurality of multi-bit confidence levels.
10. The method of claim 8 , wherein generating the plurality of compressed confidence levels includes generating, by the circuit, an indicator value by combining each confidence level of the plurality of multi-bit confidence levels using a logical-AND.
11. The method of claim 10 , further comprising, transferring the plurality of values to the controller via a data bus.
12. The method of claim 11 , further comprising sending, by the circuit, the indicator value to the controller using at least one wire separate from the data bus.
13. The method of claim 7 , wherein each memory cell of the plurality of memory cells includes a non-volatile memory cell.
14. A system, comprising:
a memory controller; and
a memory coupled to the memory controller via a data bus, wherein the memory includes a plurality of memory cells, and wherein the memory is configured to:
read a plurality of values from a subset of the plurality of memory cells using a threshold value, wherein a particular value of the plurality of values is indicative of data stored in a particular memory cell of the subset of the plurality of memory cells;
determine a plurality of multi-bit confidence levels using the plurality of values, wherein a particular multi-bit confidence level of the plurality of multi-bit confidence levels is indicative of a difference between a particular value and the threshold value; and
transfer the plurality of multi-bit confidence levels to the memory controller.
15. The system of claim 14 , wherein to transfer the plurality of multi-bit confidence levels to the memory controller, the memory is further configured to generate a plurality of compressed confidence levels using the plurality of multi-bit confidence levels.
16. The system of claim 15 , wherein to generate the plurality of compressed confidence levels, the memory is further configured to run-length encode the plurality of multi-bit confidence levels.
17. The system of claim 15 , wherein to generate the plurality of compressed confidence levels, the memory is further configured to combine each confidence level of the plurality of multi-bit confidence levels using a logical-AND operation to generate an indicator value.
18. The system of claim 17 , wherein the memory is coupled to the memory controller via a data bus, and wherein the memory is further configured to transfer the plurality of values to the memory controller via the data bus.
19. The system of claim 18 , wherein the memory is further configured to send the indicator value to the memory controller using at least one wire separate from the data bus.
20. The system of claim 14 , wherein each memory cell of the plurality of memory cells includes a non-volatile memory cell.