Dynamic Random Access Memory For Communications Systems
An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, and DRAM cells. A first portion of the DRAM cells may be refreshed by the memory refresh circuit. The DRAM cells store data received via a communication link and a rate at which the first portion of the DRAM cells is refreshed may be adjusted based on a symbol rate at which the data is received via the communication link. The DRAM cells may include one-transistor (“1T”) cells. The adjustment of the rate at which the first portion of the DRAM cells is refreshed may include an enabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a first time interval and a disabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a second time interval.
1 . A system comprising:
an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and dynamic random access memory (DRAM) cells, wherein:
a first portion of said DRAM cells is refreshed by said memory refresh circuit;
said DRAM cells store data received via a communication link; and
a rate at which said first portion of said DRAM cells is refreshed is adjusted based on a symbol rate at which said data is received via said communication link.
2 . The system of claim 1 , wherein said DRAM cells comprise one-transistor (“1T”) cells.
3 . The system of claim 1 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises an enabling of refresh of said first portion of said DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said first portion of said DRAM cells by said memory refresh circuit during a second time interval.
4 . The system of claim 1 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed is based on a forward error correction code rate of said data.
5 . The system of claim 1 , wherein:
said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises a disabling of refresh of said first portion of said DRAM cells when said symbol rate is above a determined threshold; and
said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises an enabling of refresh of said first portion of said DRAM cells when said symbol rate is below said determined threshold.
6 . The system of claim 1 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed is performed during run-time of said integrated circuit.
7 . A system comprising:
an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and dynamic random access memory (DRAM) cells, wherein:
a first portion of said DRAM cells is refreshed by said memory refresh circuit; and
a rate at which said first portion of said DRAM cells is refreshed is adjusted based on a non-zero error tolerance of data stored in said first portion of said DRAM cells.
8 . The system of claim 7 , wherein said DRAM cells comprise one-transistor (“1T”) cells.
9 . The system of claim 7 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises an enabling of refresh of said first portion of said DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said first portion of said DRAM cells by said memory refresh circuit during a second time interval.
10 . The system of claim 7 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed is based on a forward error correction code rate of said data.
11 . The system of claim 7 , wherein:
said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises a disabling of refresh of said first portion of said DRAM cells when said error tolerance is above a determined threshold; and
said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises an enabling of refresh of said first portion of said DRAM cells when said symbol rate is below said determined threshold
12 . The system of claim 7 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed is performed during run-time of said integrated circuit.
13 . A system comprising:
an integrated circuit comprising a digital logic circuit, a memory refresh circuit, and dynamic random access memory (DRAM) cells, wherein:
a first portion of said DRAM cells is refreshed by said memory refresh circuit; and
a rate at which said first portion of said DRAM cells is refreshed is adjusted based on a forward error correction code rate of data stored in said first portion of said DRAM cells.
14 . The system of claim 13 , wherein said DRAM cells comprise one-transistor (“1T”) cells.
15 . The system of claim 13 , wherein said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises an enabling of refresh of said first portion of said DRAM cells by said memory refresh circuit during a first time interval and a disabling of refresh of said first portion of said DRAM cells by said memory refresh circuit during a second time interval.
16 . The system of claim 13 , wherein:
said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises a disabling of refresh of said first portion of said DRAM cells when said error tolerance is above a determined threshold; and
said adjustment of said rate at which said first portion of said DRAM cells is refreshed comprises an enabling of refresh of said first portion of said DRAM cells when said symbol rate is below said determined threshold
17 . The system of claim 13 , wherein said adjustment is performed during run-time of said integrated circuit.