IP Library Granted Patent US 10,014,871
Granted Patent B2
US 10,014,871 · App. 15/605,469 · Granted Jul 3, 2018

Asynchronous successive approximation analog-to-digital converter and related methods and apparatus

Inventors: Kailiang Chen (Guilford, CT); Tyler S. Ralston (Clinton, CT)
Assignee: Butterfly Network, Inc.
H03M1/002A61B8/4494H03M1/125H03M1/462
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Quick Facts
Patent No.
US 10,014,871
App. No.
15/605,469
Granted
Jul 3, 2018
Kind
B2
Abstract

An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Claims (22)

1. An apparatus, comprising:

an ultrasonic transducer;

a receive circuitry coupled to the ultrasonic transducer, the receive circuitry providing an analog signal to represent information relating to an ultrasound image;

an Analog-to-Digital Converter (ADC) to communicate with the receive circuitry, the ADC further comprising a Successive Approximation Register (SAR) Controller, the ADC configured to receive the analog signal, a first clock signal and a second clock signal and output a digital representation of the analog signal;

wherein:

the first clock signal and the second clock signal govern timing of successive analog-to-digital conversions;

the first and the second clock signals are independent of a high-speed clock signal;

the SAR Controller is configured to successively approximate a quantification value for one bit per clock cycle, proceeding from the most significant bit (MSB) to the least significant bit (LSB); and

conversion of the MSB is triggered by the second clock signal.

2. The apparatus of claim 1 , wherein the digital representation of the analog signal comprises a digital word of N bits, wherein N is between 5 and 20.

3. The apparatus of claim 1 , wherein conversion of subsequent bits of the SAR ADC is triggered by a signal subsequent to a previous conversion.

4. The apparatus of claim 1 , wherein the ultrasonic transducer is part of an array of M×N ultrasonic transducers.

5. A method to detect an ultrasound signal, comprising:

receiving a first plurality of ultrasound signals from a body, the first plurality of ultrasound signals defining an analog signal;

averaging the first plurality of ultrasound signals to obtain a first average signal; and

digitizing the first average signal at an Analog-to-Digital Converter (ADC) by successive approximation of a quantized representation of the first average signal by iteratively decreasing an error signal associated with the analog signal;

wherein the successive approximation of the quantized representation for at least one bit of data is an asynchronous successive approximation independent of a clock cycle; and

wherein at least one step of iteratively decreasing the error signal is triggered by completion of a prior iteration cycle.

6. The method of claim 5 , wherein a first conversion cycle of the successive approximation is triggered by a first clock cycle and a subsequent conversion cycle of the successive approximation is triggered by completion of the first conversion cycle.

7. The method of claim 5 , wherein the step of averaging the first plurality of ultrasound signals further comprises summing the first plurality of ultrasound signals to provide a summed analog signal.

8. The method of claim 7 , further comprising receiving and holding the summed analog signal for one clock cycle.

9. The method of claim 7 , further comprising converting a successive approximation word to an equivalent analog signal to produce a control for comparing against the summed analog signal.

Assignments (2)
CHANGE OF NAME Recorded Mar 16, 2022
From: BUTTERFLY NETWORK, INC.
To: BFLY OPERATIONS, INC.
Reel/Frame 059369/0969 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2017
From: CHEN, KAILIANG; RALSTON, TYLER S.
To: BUTTERFLY NETWORK, INC.
Reel/Frame 042513/0710 →
Continuity (2)
Continuation 14957418 · Dec 2, 2015
Related Publication 20170264307A1 · Sep 14, 2017
Cited By (2)
US 12,231,097 US 12,616,445