High voltage galvanic isolation device
A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
1. An integrated circuit, comprising:
a substrate;
a lower conductive plate above the substrate;
a first dielectric layer above the lower conductive plate, the first dielectric layer having a first bandgap energy;
a second dielectric layer having a second bandgap energy lower than the first bandgap energy, the second dielectric layer including a first sub-layer above the first dielectric layer, and a second sub-layer above the first sub-layer;
an isolation break extending into the second sub-layer and terminated near the first sub-layer, the isolation break dividing the second sub-layer into:
a first portion co-extending with the lower conductive plate; and
a second portion free of overlapping with the lower conductive plate; and
an upper conductive plate above the second sub-layer and circumscribed by the isolation break.
2. The integrated circuit of claim 1 , wherein:
the first sub-layer having the second bandgap energy; and
the second sub-layer having a third bandgap energy lower than the second bandgap energy.
3. The integrated circuit of claim 1 , wherein the second dielectric layer includes a silicon nitride layer.
4. The integrated circuit of claim 1 , wherein the second dielectric layer includes a silicon oxynitride layer.
5. The integrated circuit of claim 1 , wherein the second dielectric layer includes:
a silicon oxynitride layer on the first dielectric layer;
a silicon nitride layer on the silicon oxynitride layer.
6. The integrated circuit of claim 1 , wherein the first portion of the second sub-layer extends beyond the lower conductive plate.
7. The integrated circuit of claim 1 , wherein the first dielectric layer has a thickness of at least 2 microns.
8. The integrated circuit of claim 1 , wherein the upper conductive plate is smaller than the lower conductive plate.
9. The integrated circuit of claim 1 , wherein the upper conductive plate sized equally with the lower conductive plate.
10. The integrated circuit of claim 1 , further comprising:
a circuit under the second portion of the second sub-layer, the circuit coupled to an interconnect layer for receiving a first voltage; and
a bond pad on the upper conductive plate for receiving a second voltage substantially higher than the first voltage.
11. The integrated circuit of claim 1 , wherein the first portion of the second sub-layer extends beyond the lower conductive plate.
12. The integrated circuit of claim 1 , wherein the first portion of the second sub-layer has a thickness and extends beyond the upper conductive plate by at least a distance twice of the thickness.
13. The integrated circuit of claim 1 , wherein:
the first sub-layer having the second bandgap energy; and
the second sub-layer having a third bandgap energy lower than the second bandgap energy.
14. An integrated circuit, comprising:
a substrate;
a lower conductive plate above the substrate;
a first dielectric layer above the lower conductive plate, the first dielectric layer having a first bandgap energy;
a second dielectric layer having a second bandgap energy lower than the first bandgap energy, the second dielectric layer including:
a first sub-layer above the first dielectric layer and contiguously coextending with the first dielectric layer; and
a second sub-layer on the first sub-layer, the second sub-layer segregated into a first portion co-extending with the lower conductive plate, and a second portion free of overlapping with the lower conductive plate and spaced apart from the first portion; and
an upper conductive plate above and within the first portion the second dielectric layer.
15. The integrated circuit of claim 11 , wherein the second dielectric layer includes a silicon nitride layer.
16. The integrated circuit of claim 11 , wherein the second dielectric layer includes a silicon oxynitride layer.
17. The integrated circuit of claim 11 , wherein the second dielectric layer includes:
a silicon oxynitride layer on the first dielectric layer;
a silicon nitride layer on the silicon oxynitride layer.
18. The integrated circuit of claim 11 , wherein the first dielectric layer has a thickness of at least 2 microns.
19. The integrated circuit of claim 11 , further comprising:
a circuit under the second portion of the second sub-layer, the circuit coupled to an interconnect layer for receiving a first voltage; and
a bond pad on the upper conductive plate for receiving a second voltage substantially higher than the first voltage.
20. The integrated circuit of claim 11 , further comprising:
an isolation break laterally surrounding the first portion of the second sub-layer and isolating the first portion of the second sub-layer from the second portion of the second sub-layer, the isolation break having a third bandgap energy higher than the second bandgap energy.