System and method for I/O aware processor configuration
An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z−X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.
1. An information handling system, comprising:
an input/output (I/O) device;
a processor including a plurality of processor dies configured in a non-uniform memory access architecture, the processor dies including a first processor die having X processor cores and a first serial interface, wherein X is an integer number greater than one, and the first processor die is connected to the I/O device via the first serial interface, and the processor dies further including a second processor die including Y processor cores and a second serial interface, wherein Y is an integer number greater than one, the second processor die is coupled to the first processor die, and the second processor die is not connected to the I/O device via the second serial interface; and
a memory device that includes boot process logic code that:
determines that the first processor die is connected to the I/O device and that the second processor die is not connected to the I/O device;
determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y; and
enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z X, on the second processor die, based upon the determination that the second processor die is not connected to the I/O device via the second serial interface.
2. The information handling system of claim 1 , wherein the second processor die is coupled to the first processor die via a Global Memory Interconnect (GMI).
3. The information handling system of claim 1 , wherein X and Y are equal to 8.
4. The information handling system of claim 1 , wherein the first processor die is connected to the I/O device via a serial data interface.
5. The information handling system of claim 4 , wherein the serial data interface comprises a x16 Peripheral Component Interconnect-Express (PCIe) interface.
6. The information handling system of claim 1 , wherein the operating environment comprises one of a system Basic Input/Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), an Operating System (OS), and an application.
7. A method, comprising:
connecting a first processor die of a plurality of processor dies of a processor of an information handling system to an input/output (I/O) device via a first serial interface of the first processor die, wherein the processor dies are configured in a non-uniform memory access architecture, and wherein the first processor die includes X processor cores, X being an integer number greater than one;
coupling a second processor die of the processor dies to the first processor die, wherein the second processor die includes Y processor cores, Y being an integer number greater than one, and wherein the second processor die is not connected to the I/O device;
determining, by the information handling system, that the first processor die is connected to the I/O device and that the second processor die is not connected to the I/O device;
determining, by the information handling system, that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y; and
enabling, by the information handling system, the Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z X, on the second processor die, based upon the determination that the second processor die is not connected to the I/O device.
8. The method of claim 7 , wherein the second processor die is coupled to the first processor die via a Global Memory Interconnect (GMI).
9. The method of claim 7 , wherein X and Y are equal to 8.
10. The method of claim 7 , wherein the first processor die is connected to the I/O device via a serial data interface.
11. The method of claim 10 , wherein the serial data interface comprises a x16 Peripheral Component Interconnect-Express (PCIe) interface.
12. The method of claim 7 , wherein the operating environment comprises one of a system Basic Input/Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), an Operating System (OS), and an application.
13. An information handling system, comprising:
an input/output (I/O) device; and
a processor including a plurality of processor dies configured in a non-uniform memory access architecture, the processor dies including a first processor die having X processor cores and a first serial interface, wherein X is an integer number greater than one, and the first processor die is connected to the I/O device via the first serial interface, and the processor dies further including a second processor die including Y processor cores and a second serial interface, wherein Y is an integer number greater than one, the second processor die is coupled to the first processor die, and the second processor die is not connected to the I/O device via the second serial interface; and
the processor configured to:
determine that the first processor die is connected to the I/O device and that the second processor die is not connected to the I/O device;
determine that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y; and
enable Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z−X, on the second processor die, based upon the determination that the second processor die is not connected to the I/O device via the second serial interface.
14. The information handling system of claim 13 , wherein the second processor die is coupled to the first processor die via a Global Memory Interconnect (GMI).
15. The information handling system of claim 13 , wherein X and Y are equal to 8.
16. The information handling system of claim 13 , wherein the first processor die is connected to the I/O device via a serial data interface.
17. The information handling system of claim 16 , wherein the serial data interface comprises an x16 Peripheral Component Interconnect-Express (PCIe) interface.
18. The information handling system of claim 13 , wherein the operating environment comprises one of a system Basic Input/Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), an Operating System (OS), and an application.