IP Library Granted Patent US 10,148,238
Granted Patent B2
US 10,148,238 · App. 15/608,182 · Granted Dec 4, 2018

Amplifier circuit and multipath nested miller amplifier circuit

Inventors: Masakazu Sugiura (Chiba, JP); Toshiyuki Tsuzaki (Chiba, JP); Yuji Shiine (Chiba, JP); Manabu Fujimura (Chiba, JP)
Assignee: ABLIC INC.
H03F3/45977H03F1/083H03F3/005H03F3/45H03F3/45475
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Quick Facts
Patent No.
US 10,148,238
App. No.
15/608,182
Granted
Dec 4, 2018
Kind
B2
Abstract

Provided are an amplifier circuit capable of reducing DC offset voltage without an increase in chip area and degradation in frequency characteristics, and a multipath nested miller amplifier circuit. The amplifier circuit includes a chopper switching circuit, a sampling circuit configured to sample an output signal from the chopper switching circuit, and a holding circuit configured to hold a signal output from the sampling circuit.

Claims (18)

1. An amplifier circuit configured to amplify an input signal, comprising:

a chopper switching circuit configured to provide a modulated signal of the input signal in one of a positive phase and a negative phase;

a voltage-to-current conversion circuit connected to the chopper switching circuit, and configured to generate an output current according to an output voltage from the chopper switching circuit;

a sampling circuit connected to the voltage-to-current conversion circuit including a pair of capacitors having a same capacitance value, and the sampling circuit configured to:

sample electric charges according to the output current from the voltage-to-current conversion circuit; and

provide a voltage according to an electric charge obtained by one of addition and subtraction of the sampled electric charges across the pair of capacitors; and

a holding circuit connected to the sampling circuit, and configured to hold the voltage output from the sampling circuit.

2. The amplifier circuit according to claim 1 , wherein the sampling circuit is further configured to:

perform an operation of one of the addition and the subtraction of the sampled electric charges by parallel connection of the pair of capacitors; and

provide, in synchronization with the operation, a voltage according to the electric charge subjected to one of the addition and the subtraction with the pair of capacitors connected to the holding circuit.

3. The amplifier circuit according to claim 2 , wherein the pair of capacitors comprises:

a first capacitor configured to sample an electric charge according to the output current from the voltage-to-current conversion circuit when the chopper switching circuit provides the input signal in the positive phase relationship; and

a second capacitor configured to sample the electric charge according to the output current from the voltage-to-current conversion circuit when the chopper switching circuit provides the input signal in the negative phase relationship.

4. A multipath nested miller amplifier circuit, comprising:

the amplifier circuit of claim 1 connected to an input terminal of the multipath nested miller amplifier circuit;

a first amplifier connected to an output terminal of the amplifier circuit;

a second amplifier connected to an input terminal of the amplifier circuit; and

a third amplifier connected to an output terminal of the first amplifier and an output terminal of the second amplifier.

Assignments (3)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2017
From: SUGIURA, MASAKAZU; TSUZAKI, TOSHIYUKI; SHIINE, YUJI; FUJIMURA, MANABU
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 042531/0780 →
Priority Claims (1)
JP 2016-111232 · Jun 2, 2016 · national
Continuity (1)
Related Publication 20170353166A1 · Dec 7, 2017