IP Library Granted Patent US 10,476,020
Granted Patent B2
US 10,476,020 · App. 15/608,479 · Granted Nov 12, 2019

Display device

Inventors: Kohei Kurata (Tokyo, JP); Satoshi Maruyama (Tokyo, JP)
Assignee: Japan Display Inc.
H01L51/5012H01L27/1222H01L27/1225H01L27/1248H01L27/32H01L27/3258H01L27/3262H01L51/52
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Quick Facts
Patent No.
US 10,476,020
App. No.
15/608,479
Granted
Nov 12, 2019
Kind
B2
Abstract

A display device according to the present invention includes a substrate, and a plurality of pixels arranged in the substrate, wherein each of the plurality of pixels includes a light emitting element, a first transistor, a second transistor, a first insulation layer and a second insulation layer, the first transistor includes a first semiconductor layer, the second transistor includes a second semiconductor layer, the first insulation layer is arranged across the plurality of pixels between the first semiconductor layer and the second semiconductor layer, the second insulation layer is arranged between the first insulation layer and the second semiconductor layer, the first semiconductor layer is arranged on the substrate side sandwiching the first insulation layer with respect to the second semiconductor layer, the first insulation layer includes a silicon oxide layer; and the second insulation layer includes an aluminum oxide layer.

Claims (26)

1. A display device comprising:

a substrate;

a first insulation layer, a second insulation layer, and a third insulation layer arranged over the substrate; and

a plurality of pixels arranged in the substrate;

wherein

each of the plurality of pixels includes a light emitting element, a first transistor, and a second transistor;

the first transistor includes a first semiconductor layer, a first gate electrode, and a first gate insulation layer, and

the second transistor includes a second semiconductor layer, a second gate electrode, and a second gate insulation layer,

wherein

the first insulation layer and second insulation layer are arranged between layers where the first transistor is provided and other layers where the second transistor is provided,

the first semiconductor layer is arranged between the substrate and the first insulation layer,

the second semiconductor layer is arranged over a first surface of the first insulation layer, wherein the first surface is opposite to a second surface of the first insulation layer, which faces the first semiconductor layer,

the second insulation layer is arranged between the first insulation layer and the second semiconductor layer,

the third insulation layer is arranged over a first surface of the second semiconductor layer, wherein the first surface is opposite to a second surface of the second semiconductor layer, which faces the second insulation layer,

the second gate electrode, the second gate insulation layer, and the second semiconductor layer are arranged between the second insulation layer and the third insulation layer, and

the third insulation layer is arranged in contact with the second gate electrode, and an end part of the third insulation layer is arranged on the second gate insulation layer,

the first insulation layer includes a silicon nitride layer and a silicon oxide layer in this order from the lower layer;

the second insulation layer and the third insulation layer include an aluminum oxide layer, and

the first transistor does not overlap the second transistor and the third insulation layer in planar view.

2. The display device according to claim 1 , wherein the first semiconductor layer is a polycrystal silicon layer and the second semiconductor layer is a semiconductor oxide layer.

3. The display device according to claim 1 , wherein the first transistor is a drive transistor and the second transistor is a selection transistor.

4. The display device according to claim 1 , wherein the second transistor has a top-gate structure.

5. The display device according to claim 1 , wherein the second insulation layer is arranged across at least a channel region of the second semiconductor layer.

6. The display device according to claim 1 , wherein the second insulation layer is arranged across the entire lower surface of the second semiconductor layer.

7. The display device according to claim 1 , wherein the second insulation layer does not overlap with the first semiconductor layer.

8. The display device according to claim 1 , wherein each of the plurality of pixels further includes a bank over the third insulation layer, the end part of the third insulation layer overlaps the bank in planar view.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 30, 2017
From: KURATA, KOHEI; MARUYAMA, SATOSHI
To: JAPAN DISPLAY INC.
Reel/Frame 042532/0207 →
Priority Claims (1)
JP 2016-140377 · Jul 15, 2016 · national
Continuity (1)
Related Publication 20180019431A1 · Jan 18, 2018
Cited By (3)
US 12,501,707 US 12,527,162 US 12,628,427