IP Library Granted Patent US 10,310,690
Granted Patent B2
US 10,310,690 · App. 15/609,880 · Granted Jun 4, 2019

Array substrate, display apparatus, and method of inspecting sensor electrode

Inventor: Toshiaki Fukushima (Tokyo, JP)
Assignee: Japan Display Inc.
G06F3/044G02F1/1368G02F1/13338G02F1/13458G02F1/136286G06F3/0412G06F3/0416G02F2201/121G02F2201/123G06F2203/04105
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Quick Facts
Patent No.
US 10,310,690
App. No.
15/609,880
Granted
Jun 4, 2019
Kind
B2
Abstract

According to an aspect, an array substrate includes: a substrate; a sensor electrode disposed on the substrate, and configured to detect change of capacitance; and a pull-out line capable of being electrically coupled with the sensor electrode, and pulled out to an end portion of the substrate.

Claims (53)

1. An array substrate comprising:

a substrate;

a sensor electrode disposed on the substrate, and configured to detect change of capacitance; and

a pull-out line capable of being electrically coupled with the sensor electrode, and pulled out to an end portion of the substrate,

a plurality of pads for external coupling arranged in a frame region of the substrate; and

a frame line configured to couple the sensor electrode and one of the pads for external coupling with each other, wherein

the pull-out line is coupled with the sensor electrode through the frame line and one of the external coupling pads, and

an array pitch of the pads for external coupling falls within a range of 0.02 mm to 0.6 mm.

2. The array substrate according to claim 1 , wherein the pull-out line includes a metal layer.

3. The array substrate according to claim 2 , further comprising:

a gate line; and

a source line, wherein

the metal layer includes a metal material identical to a metal material included in the gate line or the source line.

4. The array substrate according to claim 2 , further comprising:

a gate line; and

a source line, wherein

the metal layer is a layer identical to a layer of the gate line or the source line.

5. The array substrate according to claim 2 , wherein

the metal layer of the pull-out line is exposed at a cut surface of the end portion of the substrate.

6. The array substrate according to claim 1 , further comprising:

a pixel electrode;

a gate line;

a source line; and

a plurality of pads for display inspection configured to inspect one of the pixel electrode, the gate line, and the source line, wherein

an array pitch of the pads for external coupling is smaller than an array pitch of the pads for display inspection.

7. The array substrate according to claim 1 , further comprising a light-transmissive conductive layer on an uppermost surface of each of the pads for external coupling.

8. A display apparatus in which the array substrate according to claim 1 and a counter substrate are bonded together.

9. An array substrate comprising:

a substrate;

a sensor electrode disposed on the substrate, and configured to detect change of capacitance;

a pull-out line capable of being electrically coupled with the sensor electrode, and pulled out to an end portion of the substrate;

a plurality of pads for external coupling arranged in a frame region of the substrate; and

a frame line configured to couple the sensor electrode and one of the pads for external coupling with each other, wherein

the pull-out line is coupled with the sensor electrode through the frame line and one of the external coupling pads, and

a width of each of the pad for external coupling falls within a range of 0.01 mm to 0.50 mm.

10. The array substrate according to claim 9 , wherein the pull-out line includes a metal layer.

11. The array substrate according to claim 10 , further comprising:

a gate line; and

a source line, wherein

the metal layer includes a metal material identical to a metal material included in the gate line or the source line.

12. The array substrate according to claim 10 , further comprising:

a gate line; and

a source line, wherein

the metal layer is a layer identical to a layer of the gate line or the source line.

13. The array substrate according to claim 10 , wherein

the metal layer of the pull-out line is exposed at a cut surface of the end portion of the substrate.

14. The array substrate according to claim 9 , further comprising: a pixel electrode;

a gate line;

a source line; and

a plurality of pads for display inspection configured to inspect one of the pixel electrode, the gate line, and the source line, wherein

an array pitch of the pads for external coupling is smaller than an array pitch of the pads for display inspection.

15. The array substrate according to claim 9 , further comprising a light-transmissive conductive layer on an uppermost surface of each of the pads for external coupling.

16. A display apparatus in which the array substrate according to claim 9 and a counter substrate are bonded together.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2026
From: MAGNOLIA WHITE CORPORATION
To: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 074188/0280 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2017
From: FUKUSHIMA, TOSHIAKI
To: JAPAN DISPLAY INC.
Reel/Frame 042548/0273 →
Priority Claims (1)
JP 2016-124947 · Jun 23, 2016 · national
Continuity (1)
Related Publication 20170371447A1 · Dec 28, 2017