IP Library Granted Patent US 10,020,637
Granted Patent B2
US 10,020,637 · App. 15/611,268 · Granted Jul 10, 2018

Method for manufacturing semiconductor device and semiconductor device

Inventors: Satoshi Ae (Tokyo, JP); Shoutarou Kitamura (Tokyo, JP); Tetsuro Okuda (Tokyo, JP); Suguru Kato (Tokyo, JP); Isao Watanabe (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01S5/3202H01S5/2272H01S5/2201H01S5/2224H01S5/34313H01S2304/04
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Quick Facts
Patent No.
US 10,020,637
App. No.
15/611,268
Granted
Jul 10, 2018
Kind
B2
Abstract

To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.

Claims (26)

1. A method for manufacturing a semiconductor device, comprising steps of:

(a) forming a mask in a region that separates a first region and a second region of a substrate;

(b) growing a first semiconductor layer in the first region of the substrate and growing a third semiconductor layer in the second region of the substrate; and

(c) growing a second semiconductor layer over the first semiconductor layer and growing a fourth semiconductor layer over the third semiconductor layer,

wherein the substrate inclines by an angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane,

wherein the substrate, the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer are comprised of group III-V compound semiconductors,

wherein the substrate, the second semiconductor layer and the fourth semiconductor layer are comprised of InP, and the first semiconductor layer and the third semiconductor layer are comprised of InGaAlAs,

wherein side faces of the second semiconductor layer each have a (0-11) plane,

wherein a second lamination part is arranged being separated from a first lamination part of the first semiconductor layer and the second semiconductor layer,

wherein the second lamination part has the third semiconductor layer and the fourth semiconductor layer, and

wherein a thickness of the first semiconductor layer is larger than a thickness of the third semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the step (c) is a step of forming the second semiconductor layer by epitaxial growth using a source gas of a group III element and a source gas of a group V element, and

wherein a V/III ratio that is a ratio of a flow rate of the source gas of the group V element to a flow rate of the source gas of the group III element is 2000 or more.

3. The method for manufacturing a semiconductor device according to claim 1 , further comprising a step (d) of:

forming a first electrode above the second semiconductor layer and the fourth semiconductor layer after the step (c) and forming a second electrode over a rear face of the substrate.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the first lamination part and the second lamination part extend in a first direction, and wherein a sectional shape of the first lamination part, in a second direction intersecting the first direction, is an approximately rectangular shape.

5. The method for manufacturing a semiconductor device according to claim 1 ,

wherein side faces of the first lamination part of the first semiconductor layer and the second semiconductor layer are almost perpendicular to the (100) plane.

6. The method for manufacturing a semiconductor device according to claim 1 ,

wherein the first semiconductor layer and the second semiconductor layer extend in a first direction, and

wherein a width of a top face of the second semiconductor layer in a second direction intersecting the first direction is larger than a width of a top face of the first semiconductor layer in the second direction.

7. The method for manufacturing a semiconductor device according to claim 3 , further comprising a step of:

(e) forming a semi-insulating layer that has insulation from the first lamination part on both sides of the first lamination part, and has insulation from the second lamination part on both sides of the second lamination part, between the step (c) and the step (d).

8. The method for manufacturing a semiconductor device according to claim 7 ,

wherein the semi-insulating layer is comprised of InP containing Fe.

Assignments (1)
CHANGE OF ADDRESS OF ASSIGNEE Recorded Jun 1, 2018
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 045984/0759 →
Priority Claims (1)
JP 2013-196093 · Sep 20, 2013 · national
Continuity (2)
Division 14491798 · Sep 19, 2014
Related Publication 20170271848A1 · Sep 21, 2017