DATA STORAGE IN DEGRADED SOLID STATE MEMORY
Technologies are generally described for systems, devices, and methods effective to operate a memory device. A memory controller may compress initial data to produce compressed data. The memory controller may select a storage block in the memory device. The memory controller may identify one or more positions of defective cells in the selected storage block. The memory controller may manipulate the compressed data based on the identified one or more positions to produce manipulated data. The memory controller may store the manipulated data in the selected storage block.
1 . A method to operate a memory device, the method comprising:
identifying a speed used to write to the memory device;
identifying a number of errors associated with the identified speed;
identifying an error correction code level of an error correction code module;
selecting a storage block in the memory device with a number of defective cells, wherein the storage block is selected based on the identified error correction code level, the identified number of errors associated with the identified speed, and the number of defective cells; and
writing to the selected storage block at the identified speed.
2 . The method of claim 1 , wherein selecting the storage block includes determining that the number of defective cells in the selected storage block is less than a number of correctable errors defined by the identified error correction code level.
3 . The method of claim 1 , wherein selecting the storage block includes determining that a number of correctable errors defined by the identified error correction code level is greater than a sum of the number of defective cells in the selected storage block and the identified number of errors associated with the identified speed.
4 . The method of claim 1 , wherein identifying the speed includes identifying the speed based on a workload intensity during business hours of a day and non-business hours of the day.
5 . The method of claim 1 , wherein the identified speed is proportional to the number of errors.
6 . The method of claim 1 , wherein the number of errors associated with the identified speed includes a number of correctable write errors for a specific time period.
7 . The method of claim 1 , wherein identifying the number of errors associated with the identified speed includes identifying the number of errors from a table, wherein the table associates a particular write speed with a particular number of write errors per unit time.
8 . A memory device, comprising:
a memory controller; and
a memory chip configured to be in communication with the memory controller, wherein the memory controller is effective to perform, or to cause one or more other devices to be effective to perform:
identify a speed used to write to the memory chip;
identify a number of errors associated with the identified speed;
identify an error correction code level of an error correction code module;
select a storage block in the memory chip with a number of defective cells based on the identified error correction code level, the identified number of errors associated with the identified speed, and the number of defective cells; and
write to the selected storage block.
9 . The memory device of claim 8 , wherein the selection of the storage block includes a determination that the number of defective cells in the selected storage block is less than a number of correctable errors defined by the identified error correction code level.
10 . The memory device of claim 8 , wherein the selection of the storage block includes a determination that a number of correctable errors defined by the identified error correction code level is greater than a sum of the number of defective cells and the identified number of errors associated with the speed.
11 . The memory device of claim 8 , wherein the identification of the speed is based on workload intensity during business hours of a day and the non-business hours of the day.
12 . The memory device of claim 8 , wherein the identified speed is proportional to the number of errors.
13 . The memory device of claim 8 , wherein the number of errors associated with the identified speed includes a number of correctable write errors for a specific time period.
14 . The memory device of claim 8 , wherein the number of errors associated with the identified speed are identified from a table, and wherein the table associates a particular write speed with a particular number of write errors per unit time.
15 . The memory device of claim 8 , wherein the error correction module is configured to correct a certain number or certain percentage of memory write and/or read errors.
16 . A method to operate a memory device, the method comprising:
identifying a speed used to write to the memory device;
identifying an error correction code level of an error correction code module in the memory device; and
selecting, based on the identified speed, a storage block with a number of defective cells in the memory device, wherein the number of defective cells in the selected storage block is less than a number of correctable errors defined by the identified error correction code level.
17 . The method of claim 16 , wherein identifying the speed includes identifying a speed that is proportional to a number of errors associated with the identified speed, and wherein the number of errors associated with the identified speed includes a number of correctable write errors for a specific time period.
18 . The method of claim 17 , wherein the number of errors associated with the identified speed are identified from a table, and wherein the table associates a particular write speed with a particular number of write errors per unit time.
19 . The method of claim 17 , wherein identifying the error correction code level includes identifying an error correction code level that is greater than the number of errors associated with the identified speed.
20 . The method of claim 16 , wherein identifying the speed includes identifying the speed based on a workload intensity during business hours of a day and non-business hours of the day.