PARASITIC CHANNEL MITIGATION USING RARE-EARTH OXIDE AND/OR RARE-EARTH NITRIDE DIFFUSION BARRIER REGIONS
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
1 . A semiconductor structure, comprising:
a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm;
a diffusion barrier region comprising a rare-earth oxide and/or a rare-earth nitride located over a surface of the substrate; and
a III-nitride material region located over the diffusion barrier region comprising the rare-earth oxide and/or the rare-earth nitride.’
2 . The semiconductor structure of claim 1 , wherein the diffusion barrier region comprising the rare-earth oxide and/or rare-earth nitride has a thickness of less than about 200 nm.
3 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Group III species in the substrate is less than about 10 17 /cm 3 .
4 . The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm.
5 . The semiconductor structure of claim 1 , wherein the peak concentration of Al, Ga, and/or In in the substrate is less than about 10 17 /cm 3 .
6 . The semiconductor structure of claim 1 , wherein the substrate comprises a surface region associated with the surface of the substrate, and the surface region comprises a low-conductivity parasitic channel or the substrate is free of a parasitic channel.
7 . The semiconductor structure of claim 6 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 .
8 . The semiconductor structure of claim 6 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 .
9 . The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate.
10 . The semiconductor structure of claim 20 , wherein the substrate is a bulk silicon wafer.
11 . The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate.
12 . The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate.
13 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN.
14 . The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate.
15 . The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
16 . A method of forming a semiconductor structure, comprising:
forming a diffusion barrier region comprising a rare-earth oxide and/or a rare-earth nitride over a substrate comprising silicon, the substrate comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; and
forming a III-nitride material region over the diffusion barrier region comprising the rare-earth oxide and/or the rare-earth nitride.