Transposing in a matrix-vector processor

1. A circuit for transposing a matrix, the circuit comprising:

staggered memory read circuitry comprising a plurality of multiplexors, wherein the staggered memory read circuitry is configured to:

access, for each of one or more diagonals of the matrix, elements of the diagonal of the matrix; and

output, by the plurality of multiplexors and for each of the one or more diagonals of the matrix, the elements of the diagonal of the matrix in a respective first vector;

reversal circuitry configured to:

receive, from the plurality of multiplexors of the staggered memory read circuitry and for each of the one or more diagonals of the matrix, the elements of the diagonal of the matrix in the respective first vector, and

generate, for each of the one or more diagonals of the matrix, a respective second vector that includes the elements of the diagonal of the matrix in the respective first vector in an order that is a reverse of an order of the elements of the diagonal of the matrix in the respective first vector; and

rotation circuitry configured to:

determine, for each of the one or more diagonals of the matrix, a number of positions by which to rotate the elements of the diagonal of the matrix in the respective second vector,

receive, for each of the one or more diagonals of the matrix, the respective second vector of elements of the diagonal of the matrix, and

generate, for each of the one or more diagonals of the matrix, a respective third vector that includes the elements of the diagonal of the matrix in the respective second vector in an order that is a rotation of the elements of the diagonal of the matrix in the respective second vector by the determined number of positions.

2. The circuit of claim 1 , comprising:

counting circuitry configured to output, to the rotation circuitry and for each of the one or more diagonals of the matrix, the determined number of positions by which to rotate the elements of the diagonal of the matrix in the respective second vector.

3. The circuit of claim 2 , wherein the counting circuitry is configured to output, as the number of positions by which to rotate the elements of the diagonal of the matrix in the respective second vector and for each of the one or more diagonals of the matrix, a value, wherein an initial value output by the counting circuitry is equivalent to N−1, where N is equivalent to the width of the rotation circuitry.

4. The circuit of claim 3 , wherein the counting circuitry is configured to adjust the value for each of the one or more diagonals of the matrix, wherein adjusting the value comprises:

when the value is positive, decrementing the value output by the counting circuitry; and

when the value is zero, resetting the value to the initial value.

5. The circuit of claim 1 , wherein the matrix is a submatrix of a second matrix.

6. The circuit of claim 1 , wherein the plurality of multiplexors comprises M multiplexors, where M is equivalent to the width of the reversal circuitry, and wherein each multiplexor is configured to output one of a plurality of elements of a column of a matrix.

7. The circuit of claim 6 , wherein the staggered memory read circuitry is configured to receive a control signal that specifies, for each of the M multiplexors, an input of the multiplexor to provide as an output of the multiplexor.

8. The circuit of claim 6 , wherein each of the M multiplexors is an N-to-1 multiplexor, where N is the number of elements capable of being received by the rotation circuitry.

9. The circuit of claim 6 , wherein the staggered memory read circuit is configured to:

receive a first control signal that specifies, for a first one or more of the M multiplexors, an input of the multiplexor to provide as an output of the multiplexor; and

receive a second control signal that specifies, for a second one or more of the M multiplexors, an input of the multiplexor to provide as an output of the multiplexor.

10. The circuit of claim 1 , comprising:

staggered memory write circuitry configured to write, for each of the one or more diagonals of the matrix, the elements of the diagonal of the matrix in the respective third vector to memory as a diagonal of a transpose output matrix.

11. The circuit of claim 1 , wherein the matrix comprises two or more matrices stored in memory as a single matrix.

12. The circuit of claim 1 , wherein the rotation circuitry is configured to perform right rotation of the elements of the diagonal of the matrix in the respective second vector by the determined number of positions to generate the respective third vector.

13. The circuit of claim 1 , wherein the matrix is stored at a static random-access memory accessible by the circuit.

14. The circuit of claim 1 , wherein, for each of the one or more diagonals of the matrix, the elements of the diagonal of the matrix in the respective third vector are stored in a static random-access memory as a diagonal of a transpose output matrix.

15. The circuit of claim 1 , comprising second rotation circuitry configured to:

determine, for each of one or more diagonals of a second matrix, a second number of positions by which to rotate elements of the diagonal of the second matrix;

receive, for each of the one or more diagonals of the second matrix, a respective fourth vector that includes elements of the diagonal of the second matrix; and

generate, for each of the one or more diagonals of the second matrix, a respective fifth vector that includes the elements of the diagonal of the second matrix in the respective fourth vector in an order that is a rotation of the elements of the diagonal of the second matrix in the respective fourth vector by the determined second number of positions.

16. The circuit of claim 15 , comprising:

second counting circuitry configured to output, to the second rotation circuitry and for each of the one or more diagonals of the second matrix, the determined second number of positions by which to rotate the elements of the diagonal of the second matrix in the respective fourth vector.

17. A circuit for transposing an input vector, the circuit comprising:

staggered memory read circuitry comprising a plurality of multiplexors, wherein the staggered memory read circuitry is configured to:

access elements of the input vector; and

output, by the plurality of multiplexors, the elements of the input vector in a first vector:

reversal circuitry configured to:

receive the first vector that includes the elements of the input vector, and

generate a second vector that includes the elements of the first vector in an order that is a reverse of the order of the elements in the first vector; and

rotation circuitry configured to:

determine a number of positions by which to rotate the elements in the second vector,

receive the second vector of elements, and

generate a third vector that includes the elements of the second vector in an order that is a rotation of the order of the elements in the second vector by the determined number of positions.