Method of producing semiconductor chips that efficiently dissipate heat
View Patent ↗A method of producing a plurality of semiconductor chips includes a) providing a carrier substrate having a first major face and a second major face opposite the first major face; b) forming a diode structure between the first major face and the second major face, the diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage; c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.
1. A method of producing a plurality of semiconductor chips comprising:
a) providing a carrier substrate having a first major face and a second major face opposite the first major face;
b) forming a diode structure between the first major face and the second major face, said diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage;
c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and
d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips,
wherein the semiconductor layer sequence is deposited epitaxially on the carrier substrate,
the diode structure is formed over the entire area in the carrier substrate in a plane extending parallel to the first major face,
a first electric contact of the semiconductor chip is formed on the first major face of the carrier substrate such that charge carriers are injected via a first layer of the carrier substrate into the semiconductor layer sequence, and
a second electric contact of the semiconductor chip is located on a radiation exit face of the semiconductor layer sequence remote from the carrier substrate.
2. The method according to claim 1 , wherein b) is carried out before d).
3. The method according to claim 1 , wherein the diode structure is formed by full-surface doping of the carrier substrate.
4. The method according to claim 1 , wherein the diode structure comprises a first diode and a second diode, the first diode and the second diode being oppositely oriented with respect to their conducting direction.
5. The method according to claim 1 , wherein the diode structure is formed by layered doping of the carrier substrate.
6. The method according to claim 1 , wherein the diode structure comprises at least three successive layers configured alternately with respect to their conduction type.
7. The method according to claim 1 , wherein a side face of the carrier substrate is provided with a passivation layer.
8. The method according to claim 1 , wherein a protection diode is formed in the carrier substrate.
9. The method according to claim 8 , wherein the protection diode is formed between the first major face and the diode structure.