Multi-layer potting for electronic modules
View Patent ↗An electronics module, such as driver modules for LED-based lighting fixtures and the like, includes a printed circuit board (PCB), a stress mitigation layer, and a potting layer. The PCB has a plurality of vias, which extend through the printed circuit board. A plurality of electronic components may each have a body and a plurality of leads extending from the body and through corresponding ones of the plurality of vias, wherein solder joints electrically and mechanically affix the plurality of leads within the corresponding ones of the plurality of vias. The stress mitigation layer is applied over a top surface of the printed circuit board. The potting layer is applied over the stress mitigation layer and the plurality of electronic components.
1. A lighting fixture comprising:
a plurality of light emitting diodes (LEDs) responsive to a drive signal; and
a driver module configured to provide the drive signal and comprising:
a printed circuit board comprising a plurality of vias, which extend through the printed circuit board;
a plurality of electronic components that each comprise a body and a plurality of leads that extend from the body and through corresponding ones of the plurality of vias, wherein solder joints electrically and mechanically affix the plurality of leads within the corresponding ones of the plurality of vias;
a stress mitigation layer comprising a silicone gel and applied over a top surface of the printed circuit board; and
a potting layer applied over the stress mitigation layer and the plurality of electronic components, wherein an ASTM Shore hardness rating of the stress mitigation layer is less than an ASTM Shore hardness rating of the potting layer;
wherein the stress mitigation layer is between the potting layer and the solder joints.
2. The lighting fixture of claim 1 wherein the potting layer comprises silicone.
3. The lighting fixture of claim 2 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 70 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 35 and 90 on a Shore type A scale.
4. The lighting fixture of claim 2 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 40 and 85 on a Shore type A scale.
5. The lighting fixture of claim 2 wherein a modulus of elasticity of the stress mitigation layer is between 0.0005 and 0.003 mega-pascal (MPa), and a modulus of elasticity of the potting layer is between 1.0 and 5.0 MPa.
6. The lighting fixture of claim 2 wherein a modulus of elasticity of the stress mitigation layer is between 0.001 and 0.0015 mega-pascal (MPa), and a modulus of elasticity of the potting layer is between 1.0 and 5.0 MPa.
7. The lighting fixture of claim 2 wherein a thermal conductivity of the stress mitigation layer is less than 0.2 watts per meter kelvin (W/(m k), and a thermal conductivity of the potting layer is greater than 0.40 W/(m k).
8. The lighting fixture of claim 2 wherein:
at least two of the plurality of leads have clinched ends; and
the at least two of the plurality of leads are lead formed such that the at least two of the plurality of leads are formed into at least one non-linear shape between the top surface of the printed circuit board and bottom surfaces of the bodies of the plurality of electronic components, such that forces applied to the bodies of the plurality of electronic components due to expansion and contraction of the potting layer are absorbed by the at least two of the plurality of leads prior to reaching the solder joints.
9. The lighting fixture of claim 2 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 35 and 90 on a Shore type A scale.
10. The lighting fixture of claim 2 wherein at least two of the plurality of leads have clinched ends.
11. The lighting fixture of claim 2 wherein at least two of the plurality of leads are lead formed such that the at least two of the plurality of leads are formed into at least one non-linear shape between the top surface of the printed circuit board and bottom surfaces of the bodies of the plurality of electronic components, such that forces applied to the bodies of the plurality of electronic components due to expansion and contraction of the potting layer are absorbed by the at least two of the plurality of leads prior to reaching the solder joints.
12. The lighting fixture of claim 2 wherein a cavity is formed beneath at least one of the plurality of electronic components, the cavity defined by a bottom surface of the at least one of the plurality of electronic components, the top surface of the printed circuit board, and at least one sidewall of the stress mitigation layer.
13. The lighting fixture of claim 2 wherein the stress mitigation layer completely covers top surfaces of at least certain of the plurality of electronic components.
14. The lighting fixture of claim 13 wherein a cavity is formed beneath at least one of the plurality of electronic components, the cavity defined by a bottom surface of the at least one of the plurality of electronic components, the top surface of the printed circuit board, and at least one sidewall of the stress mitigation layer.
15. The lighting fixture of claim 14 wherein:
the plurality of leads have clinched ends; and
the plurality of leads are lead formed such that each of the plurality of leads is formed into at least one non-linear shape between the top surface of the printed circuit board and bottom surfaces of the bodies of the plurality of electronic components, such that forces applied to the bodies of the plurality of electronic components due to expansion and contraction of the potting layer are absorbed by the plurality of leads prior to reaching the solder joints.
16. The lighting fixture of claim 15 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 40 and 85 on a Shore type A scale.
17. The lighting fixture of claim 2 wherein the stress mitigation layer does not cover top surfaces of any of the plurality of electronic components.
18. The lighting fixture of claim 16 wherein a cavity is formed beneath at least one of the plurality of electronic components, the cavity defined by a bottom surface of the at least one of the plurality of electronic components, the top surface of the printed circuit board, and at least one sidewall of the stress mitigation layer.
19. The lighting fixture of claim 17 wherein:
the plurality of leads have clinched ends; and
the plurality of leads are lead formed such that each of the plurality of leads is formed into at least one non-linear shape between the top surface of the printed circuit board and bottom surfaces of the bodies of the plurality of electronic components, such that forces applied to the bodies of the plurality of electronic components due to expansion and contraction of the potting layer are absorbed by the plurality of leads prior to reaching the solder joints.
20. The lighting fixture of claim 19 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 40 and 85 on a Shore type A scale.
21. The lighting fixture of claim 1 wherein the solder joints withstand fracturing after 600 temperature cycles between −40 Celsius and 105 Celsius.
22. The lighting fixture of claim 2 wherein a thermal conductivity of the potting layer is greater than a thermal conductivity of the stress mitigation layer.
23. The lighting fixture of claim 2 wherein
the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 40 and 85 on a Shore type A scale; and
a thermal conductivity of the stress mitigation layer is less than 0.2 watts per meter kelvin (W/(m k), and a thermal conductivity of the potting layer is greater than 0.40 W/(m k).
24. An electronics module comprising:
a printed circuit board comprising a plurality of vias, which extend through the printed circuit board;
a plurality of electronic components that each comprise a body and a plurality of leads that extend from the body and through corresponding ones of the plurality of vias, wherein solder joints electrically and mechanically affix the plurality of leads within the corresponding ones of the plurality of vias;
a stress mitigation layer comprising a silicone gel and applied over a top surface of the printed circuit board; and
a potting layer applied over the stress mitigation layer and the plurality of electronic components, wherein an ASTM Shore hardness rating of the stress mitigation layer is less than an ASTM Shore hardness rating of the potting layer;
wherein the stress mitigation layer is between the potting layer and the solder joints.
25. The electronics module of claim 24 wherein the potting layer comprises silicone.
26. The electronics module of claim 25 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 70 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 35 and 90 on a Shore type A scale.
27. The electronics module of claim 25 wherein the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 40 and 85 on a Shore type A scale.
28. The electronics module of claim 25 wherein a modulus of elasticity of the stress mitigation layer is between 0.0005 and 0.003 mega-pascal (MPa), and a modulus of elasticity of the potting layer is between 1.0 and 5.0 MPa.
29. The electronics module of claim 25 wherein a modulus of elasticity of the stress mitigation layer is between 0.001 and 0.0015 mega-pascal (MPa), and a modulus of elasticity of the potting layer is between 1.0 and 5.0 MPa.
30. The electronics module of claim 25 wherein a thermal conductivity of the stress mitigation layer is less than 0.2 watts per meter kelvin (W/(m k), and a thermal conductivity of the potting layer is greater than 0.40 W/(m k).
31. The electronics module of claim 25 wherein:
at least two of the plurality of leads have clinched ends; and
the at least two of the plurality of leads are lead formed such that the at least two of the plurality of leads are formed into at least one non-linear shape between the top surface of the printed circuit board and bottom surfaces of the bodies of the plurality of electronic components, such that forces applied to the bodies of the plurality of electronic components due to expansion and contraction of the potting layer are absorbed by the at least two of the plurality of leads prior to reaching the solder joints.
32. The electronics module of claim 31 wherein a thermal conductivity of the potting layer is greater than a thermal conductivity of the stress mitigation layer.
33. The electronics module of claim 31 wherein
the ASTM Shore hardness rating of the stress mitigation layer is less than 65 on a Shore type 00 scale, and the ASTM Shore hardness rating of the potting layer is between 40 and 85 on a Shore type A scale; and
a thermal conductivity of the stress mitigation layer is less than 0.2 watts per meter kelvin (W/(m k), and a thermal conductivity of the potting layer is greater than 0.40 W/(m k).
34. The electronics module of claim 25 wherein at least two of the plurality of leads have clinched ends.
35. The electronics module of claim 25 wherein at least two of the plurality of leads are lead formed such that the at least two of the plurality of leads are formed into at least one non-linear shape between the top surface of the printed circuit board and bottom surfaces of the bodies of the plurality of electronic components, such that forces applied to the bodies of the plurality of electronic components due to expansion and contraction of the potting layer are absorbed by the at least two of the plurality of leads prior to reaching the solder joints.