Managing refresh for flash memory

1. A method of performing refresh operations on a Flash memory, the method comprising:

setting one or more refresh registers of the Flash memory with values received from a host; and

performing refresh operations on the Flash memory based on the values set in the one or more refresh registers, wherein setting the one or more refresh registers comprises at least one of:

setting a first register to indicate start/stop settings for the refresh operations and clearing the first register to stop an ongoing refresh operation;

setting a second register to indicate at least one partition of one or more target memory partitions of the Flash memory for the refresh operations;

setting a fourth register to indicate a refresh algorithm for performing the refresh operations; or

setting a fifth register to indicate refresh rates for performing the refresh operations.

2. The method of claim 1 , further comprising setting the second register with a special field to refresh all of the one or more target memory partitions.

3. The method of claim 1 , further comprising setting the refresh algorithm to an unselective state to refresh all data cells in a target address range for the refresh operations.

4. The method of claim 1 , further comprising setting the refresh algorithm to selectively refresh a desired portion of a target address range for the refresh operations.

5. The method of claim 1 , further comprising setting different values in the fifth register to indicate different refresh rates for different memory types in the Flash memory.

6. The method of claim 1 , further comprising setting different values in the fifth register to indicate different refresh rates for different refresh algorithms.

7. The method of claim 1 , further comprising setting different values in the fifth register to indicate different refresh rates for different temperature conditions of the Flash memory.

8. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings;

setting the second register to indicate the at least one partition;

setting the fourth register to indicate the refresh algorithm for performing the refresh operations; and

setting the fifth register to indicate the refresh rates.

9. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings; and

setting the second register to indicate the at least one partition.

10. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings; and

setting the fourth register to indicate the refresh algorithm for performing the refresh operations.

11. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings; and

setting the fifth register to indicate the refresh rates.

12. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the second register to indicate the at least one partition; and

setting the fourth register to indicate the refresh algorithm for performing the refresh operations.

13. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the second register to indicate the at least one partition; and

setting the fifth register to indicate the refresh rates.

14. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the fourth register to indicate the refresh algorithm for performing the refresh operations; and

setting the fifth register to indicate the refresh rates.

15. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings;

setting the second register to indicate the at least one partition; and

setting the fourth register to indicate the refresh algorithm for performing the refresh operations.

16. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings;

setting the second register to indicate the at least one partition; and

setting the fifth register to indicate the refresh rates.

17. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings;

setting the fourth register to indicate the refresh algorithm for performing the refresh operations; and

setting the fifth register to indicate the refresh rates.

18. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the second register to indicate the at least one partition;

setting the fourth register to indicate the refresh algorithm for performing the refresh operations; and

setting the fifth register to indicate the refresh rates.

19. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the first register to indicate the start/stop settings.

20. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the second register to indicate the at least one partition.

21. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the fourth register to indicate the refresh algorithm for performing the refresh operations.

22. The method of claim 1 , wherein setting the one or more refresh registers comprises:

setting the fifth register to indicate the refresh rates.

23. An apparatus including a Flash memory, the Flash memory comprising:

one or more refresh registers configured to be programmed with values received from a host; and

wherein the Flash memory is configured to perform refresh operations based on the values programmed in the one or more refresh registers,

wherein the one or more refresh registers comprises one or more of:

a first register configured to be programmed to indicate start/stop settings for the refresh operations, wherein the Flash memory is configured to stop an ongoing refresh operation when the first register is cleared;

a second register configured to be programmed to indicate at least one partition of one or more target memory partitions of the Flash memory for the refresh operations;

a fourth register configured to be programmed to indicate a refresh algorithm for the refresh operations to be performed on the Flash memory; or

a fifth register configured to be programmed to indicate refresh rates for performing the refresh operations.

24. The apparatus of claim 23 , wherein the Flash memory is configured to refresh all of the one or more target memory partitions when the second register is set to a special field.

25. The apparatus of claim 23 , wherein the Flash memory is configured to refresh all data cells in a target address range when the refresh algorithm is set to an unselective state.

26. The apparatus of claim 23 , wherein the Flash memory is configured to selectively refresh a desired portion of a target address range when the refresh algorithm is set to selectively refresh the desired portion of the target address range.

27. The apparatus of claim 23 integrated into a device selected from the group consisting of mobile phones, hand-held personal communication systems (PCS) units, portable data units, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, and fixed location data units.

28. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register;

the second register;

the fourth register; and

the fifth register.

29. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register; and

the second register.

30. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register; and

the fourth register.

31. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register; and

the fifth register.

32. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the second register; and

the fourth register.

33. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the second register; and

the fifth register.

34. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the fourth register; and

the fifth register.

35. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register;

the second register; and

the fourth register.

36. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register;

the second register; and

the fifth register.

37. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register;

the fourth register; and

the fifth register.

38. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the second register;

the fourth register; and

the fifth register.

39. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the first register.

40. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the second register.

41. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the fourth register.

42. The apparatus of claim 23 , wherein the one or more refresh registers comprises:

the fifth register.

43. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform refresh operations on a Flash memory, the non-transitory computer-readable storage medium comprising:

code for setting one or more refresh registers of the Flash memory with values received from a host; and

code for performing refresh operations on the Flash memory based on the values set in the one or more refresh registers,

wherein the one or more refresh registers comprises one or more of:

a first register programmable to indicate start/stop settings for the refresh operations, wherein the Flash memory is configured to stop an ongoing refresh operation when the first register is cleared;

a second register programmable to indicate at least one partition of one or more target memory partitions of the Flash memory for the refresh operations;

a fourth register programmable to indicate a refresh algorithm for the refresh operations to be performed on the Flash memory; or

a fifth register programmable to indicate refresh rates for performing the refresh operations.

44. An apparatus including a Flash memory, the Flash memory comprising:

means for storing settings received from a host, the settings associated with refresh operations to be performed on the Flash memory; and

means for performing refresh operations on the Flash memory based on the settings, wherein the means for storing settings comprises one or more of:

a first means for storing start/stop settings for the refresh operations, wherein the Flash memory is configured to stop an ongoing refresh operation when the first register is cleared;

a second means for storing settings to indicate at least one partition of one or more target memory partitions of the Flash memory for the refresh operations;

a fourth means for storing settings to indicate a refresh algorithm for the refresh operations to be performed on the Flash memory; or

a fifth means for storing settings to indicate refresh rates for performing the refresh operations.