Method of integrating a copper plating process in a through-substrate-via (TSV) on CMOS wafer
View Patent ↗A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.
1. A semiconductor device, comprising:
a semiconductor substrate having a front surface and a back surface, and comprising a metallization structure at the front surface, and an active device layer within the semiconductor substrate and adjacent to the metallization structure, the active device layer comprising doped and undoped areas of the semiconductor substrate, the metallization structure comprising first and second barrier layers spaced apart from one another; and
a copper interconnect filling a through-substrate-via (TSV) that extends through the semiconductor substrate from the back surface through the active device layer and through the first barrier layer to the second barrier layer of the metallization structure.
2. The device of claim 1 , wherein the copper interconnect fills the space between the first and second barrier layers.
3. The device of claim 2 , wherein the first and second barrier layers comprise Ti/TiN.
4. The device of claim 2 , wherein an aluminum material is situated between the first and second barrier layers, and the copper interconnect is separated from the aluminum material by a gap therebetween.
5. The device of claim 1 , further comprising an insulation layer that surrounds the copper interconnect from the back surface through the active device layer.
6. The device of claim 1 , further comprising a diffusion barrier layer that surrounds the copper interconnect from the back surface through the active device layer and the first barrier layer and lies between a bottom surface of the copper interconnect and the second barrier layer of the metallization structure.
7. The device of claim 6 , wherein the diffusion barrier layer comprises a copper seed layer.
8. The device of claim 6 , wherein the diffusion barrier layer comprises a conductive metal.
9. The device of claim 6 , wherein the diffusion barrier layer comprises a metal oxide.
10. The device of claim 1 , wherein a width of the TSV falls within a range of 5 to 30 microns.
11. The device of claim 1 , wherein a depth of the TSV measured from the back surface falls within a range of 50 to 300 microns.
12. The device of claim 1 , wherein the semiconductor substrate further comprises a bulk substrate at the back surface, the active device layer located between the bulk substrate and the metallization structure.
13. The device of claim 12 , wherein the copper interconnect filling the TSV further extends through the semiconductor substrate from the back surface through the bulk substrate.