Pixel circuit, drive method, display panel and display device
A pixel circuit, a drive method, a display panel and a display device are provided. A switch transistor is arranged between a first power supply signal and an input terminal (a source) of a drive transistor. When a drive circuit is at a second detection period during which drive current of a light emitting element is detected, the switch transistor is controlled to be turned off, such that the first power supply signal is disconnected from the source of the drive transistor. In this case, no current flows through the light emitting element, and therefore the light emitting element does not emit light, thereby solving a problem in the conventional technology that the light emitting element is lighted and it is not dark in a dark state when drive current of the pixel circuit is detected.
1. A pixel circuit, comprising
at least one pixel sub-circuit, wherein
the at least one pixel sub-circuit comprises a first switch transistor, a second switch transistor, a drive transistor, a storage capacitor and a light emitting element, wherein
the first switch transistor is controlled by a first scan signal and is configured to transmit a first data signal to a source of the drive transistor,
the second switch transistor is controlled by a second scan signal and is configured to transmit a reference voltage signal to a gate of the drive transistor,
the storage capacitor is connected in series between the gate and the source of the drive transistor and is configured to apply a charged voltage as a drive voltage of the drive transistor;
the source of the drive transistor is electrically connected to a first power supply signal, and a drain of the drive transistor is connected to an anode of the light emitting element and is configured to transmit drive current from the drive transistor to the anode of the light emitting element; and
a cathode of the light emitting element is connected to a second power supply signal, and the light emitting element emits light in response to the driving current, and wherein
the pixel circuit further comprises a third switch transistor, and the third switch transistor is controlled by a third scan signal and is configured to transmit the first power supply signal to the source of the drive transistor, wherein at a first detection period, the first switch transistor, the second switch transistor and the third switch transistor are turned off, to charge the storage capacitor by a data line; at a second detection period, the first switch transistor and the second switch transistor are turned on, and the third switch transistor is turned off, to discharging to the source of the drive transistor by the storage capacitor, and input the reference voltage signal to the gate of the drive transistor; and at a third detection period, the first switch transistor and the second switch transistor are turned off, and the third switch transistor is turned on, to input the first power supply signal to the light emitting element to control the light emitting element to emit light; or
the at least one pixel sub-circuit each further comprises a fourth switch transistor, and the fourth switch transistor is controlled by a fourth scan signal and is configured to transmit the first power supply signal to the source of the drive transistor, wherein at a first detection period, the first switch transistor and the second switch transistor are turned off, and the fourth switch transistor is turned on, to charge the storage capacitor by a data line; and at a second detection period, the first switch transistor and the second switch transistor are turned on, and the fourth switch transistor are turned off, to discharge to the source of the drive transistor by the storage capacitor, and input the reference voltage signal to the gate of the drive transistor.
2. The pixel circuit according to claim 1 , wherein
in a case that the pixel circuit further comprises the third switch transistor, a first electrode of the third switch transistor is connected to the first power supply signal, a second electrode of the third switch transistor is connected to a source of each drive transistor and a first electrode of each first switch transistor, and a gate of the third switch transistor receives the third scan signal.
3. The pixel circuit according to claim 1 , wherein
in a case that the at least one pixel sub-circuit each further comprises a fourth switch transistor, a first electrode of the fourth switch transistor is connected to the first power supply signal, a second electrode of the fourth switch transistor is connected to the source of the drive transistor and a first electrode of the first switch transistor, and a gate of the fourth switch transistor receives the fourth scan signal.
4. The pixel circuit according to claim 1 , further comprising a fifth switch transistor, wherein
a first electrode of the fifth switch transistor is connected to a third power supply signal, a second electrode of the fifth switch transistor is connected to the anode of the light emitting element, the fifth switch transistor is controlled by a fifth scan signal and is configured to transmit the third power supply signal to the anode of the light emitting element.
5. The pixel circuit according to claim 4 , wherein a potential of the reference voltage signal is higher than a potential of the third power supply signal.
6. The pixel circuit according to claim 4 , wherein each of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor is a P-type transistor or an N-type transistor.
7. The pixel circuit according to claim 1 , wherein the light emitting element is an organic light emitting diode.
8. A display panel, comprising:
pixel units arranged in an array;
a plurality of data lines for providing data signals for the pixel units;
a plurality of scan lines for providing scan signals for the pixel units; and
a plurality of reference lines for providing reference signals for the pixel units, wherein
each of the pixel units comprises a pixel circuit comprising at least one pixel sub-circuit, wherein
the at least one pixel sub-circuit comprises a first switch transistor, a second switch transistor, a drive transistor, a storage capacitor and a light emitting element,
the first switch transistor is controlled by a first scan signal and is configured to transmit a first data signal to a source of the drive transistor,
the second switch transistor is controlled by a second scan signal and is configured to transmit a reference voltage signal to a gate of the drive transistor,
the storage capacitor is connected in series between the gate and the source of the drive transistor and is configured to apply a charged voltage as a drive voltage of the drive transistor;
the source of the drive transistor is electrically connected to a first power supply signal, and a drain of the drive transistor is connected to an anode of the light emitting element and is configured to transmit drive current from the drive transistor to the anode of the light emitting element; and
a cathode of the light emitting element is connected to a second power supply signal, and the light emitting element emits light in response to the driving current, and wherein
the pixel circuit further comprises a third switch transistor, and the third switch transistor is controlled by a third scan signal and is configured to transmit the first power supply signal to the source of the drive transistor, wherein at a first detection period, the first switch transistor, the second switch transistor and the third switch transistor are turned off, to charge the storage capacitor by a data line; at a second detection period, the first switch transistor and the second switch transistor are turned on, and the third switch transistor is turned off, to discharge to the source of the drive transistor by the storage capacitor, and input the reference voltage signal to the gate of the drive transistor; and at a third detection period, the first switch transistor and the second switch transistor are turned off, and the third switch transistor is turned on, to input the first power supply signal to the light emitting element to control the light emitting element to emit light; or
the at least one pixel sub-circuit each further comprises a fourth switch transistor, and the fourth switch transistor is controlled by a fourth scan signal and is configured to transmit the first power supply signal to the source of the drive transistor, wherein at a first detection period, the first switch transistor and the second switch transistor are turned off, and the fourth switch transistor is turned on, to charge the storage capacitor by a data line; and at a second detection period, the first switch transistor and the second switch transistor are turned on, and the fourth switch transistor are turned off, to discharge to the source of the drive transistor by the storage capacitor, and input the reference voltage signal to the gate of the drive transistor;
the scan lines are parallel to a pixel row direction;
the data lines are parallel to a pixel column direction; and
in the pixel row direction, two adjacent pixel units of the pixel units share one of the data lines.
9. The display panel according to claim 8 , wherein
in a case that the pixel circuit further comprises the third switch transistor, a first electrode of the third switch transistor is connected to the first power supply signal, a second electrode of the third switch transistor is connected to a source of each drive transistor and a first electrode of each first switch transistor, and a gate of the third switch transistor receives the third scan signal.
10. The display panel according to claim 8 , wherein
in a case that the at least one pixel sub-circuit each further comprises a fourth switch transistor, a first electrode of the fourth switch transistor is connected to the first power supply signal, a second electrode of the fourth switch transistor is connected to the source of the drive transistor and a first electrode of the first switch transistor, and a gate of the fourth switch transistor receives the fourth scan signal.
11. The display panel according to claim 8 , wherein the pixel circuit further comprises a fifth switch transistor, wherein
a first electrode of the fifth switch transistor is connected to a third power supply signal, a second electrode of the fifth switch transistor is connected to the anode of the light emitting element, the fifth switch transistor is controlled by a fifth scan signal and is configured to transmit the third power supply signal to the anode of the light emitting element.
12. The display panel according to claim 11 , wherein a potential of the reference voltage signal is higher than a potential of the third power supply signal.
13. The pixel circuit according to claim 11 , wherein each of the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor is a P-type transistor or an N-type transistor.
14. The pixel circuit according to claim 8 , wherein the light emitting element is an organic light emitting diode.
15. The display panel according to claim 8 , wherein the two adjacent pixel units sharing one of the data lines are located on two sides of the shared data line, and second electrodes of the first switch transistors of the two pixel units are connected to the data line.
16. The display panel according to claim 15 , wherein gates of the first switch transistors of the two pixel units sharing one of the data lines are connected to a first scan line, gates of the second switch transistors of the two pixel units sharing one of the data lines are connected to a second scan line, and gates of the fourth switch transistors of the two pixel units sharing one of the data lines are connected to a fourth scan line.
17. The display panel according to claim 16 , further comprising
a data driver, wherein
the data driver is configured to provide a data signal for one of the two pixel units sharing one of the data lines while providing data of black or a turn-off voltage for the other of the two pixel units, to drive the two pixel units sharing one of the data lines in a time-division manner.