Interference mitigation and clock dithering for a continuous-time receiver for capacitive sensing

1. An input device, comprising:

a plurality of sensor electrodes in a sensing region of the input device; and

a processing system coupled to the plurality of sensor electrodes, the processing system configured to:

generate a first measurement of a capacitive sensing signal acquired using a first sensor electrode of the plurality of sensor electrodes during a first time period, wherein the capacitive sensing signal comprises effects of a first modulated signal driven onto at least one of the plurality of sensor electrodes, and wherein the first measurement is generated at a first sensing frequency based on a clock signal;

dither the clock signal; and

adjust a demodulation frequency based on the dithered clock signal to generate a second measurement of the capacitive sensing signal acquired using the first sensor electrode during a second time period at the first sensing frequency based on the dithered clock signal.

2. The input device of claim 1 , wherein the processing system includes a continuous-time receiver for generating the first and second measurements.

3. The input device of claim 1 , wherein the processing system is configured to dither the clock signal at every sensing burst or every sensing half-period.

4. The input device of claim 1 , wherein the processing system is configured to adjust the demodulation frequency by an amount that is inversely proportional to a value of the clock dithering.

5. The input device of claim 1 , wherein the processing system is configured to adjust the demodulation frequency by adjusting at least one of: a hardware or firmware configuration of the processing system.

6. The input device of claim 1 , wherein the processing system is configured to determine a clock dithering frequency, a value of the clock dithering, and the demodulation frequency adjustment by fetching a stored configuration indicating the clock dithering frequency, the value of the clock dithering, and the demodulation frequency adjustment.

7. A method of capacitive sensing, comprising:

driving a first modulated signal onto at least one of a plurality of sensor electrodes to acquire a capacitive sensing signal, wherein the capacitive sensing signal comprises effects of the first modulated signal on the at least one sensor electrode;

generating a first measurement of the capacitive sensing signal during a first time period, and wherein the first measurement is generated at a first sensing frequency based on a clock signal;

dithering the clock signal; and

adjusting a demodulation frequency based on the dithered clock signal to generate a second measurement of the capacitive sensing signal during a second time period at the first sensing frequency based on the dithered clock signal.

8. The method of claim 7 , wherein the demodulation comprises continuous-time demodulation.

9. The method of claim 7 , wherein the dithering is performed at every sensing burst or every sensing half-period.

10. The method of claim 7 , wherein the demodulation frequency is adjusted by an amount that is inversely proportional to a value of the clock dithering.

11. The method of claim 7 , wherein adjusting the demodulation frequency comprises adjusting at least one of: a hardware or firmware configuration of an input device.

12. The method of claim 7 , further comprising:

determining a clock dithering frequency, a value of the clock dithering, and the demodulation frequency adjustment by fetching a stored configuration indicating the clock dithering frequency, the value of the clock dithering, and the demodulation frequency adjustment.

13. A processing system for an input device, comprising:

sensor circuitry configured to drive a first modulated signal onto at least one sensor electrode of a plurality of sensor electrodes to acquire a capacitive sensing signal, wherein the capacitive sensing signal comprises effects of the first modulated signal on the at least one sensor electrodes;

a clock generator module configured to generate a clock signal; and

a determination module configured to generate a first measurement of the capacitive sensing signal during a first time period, wherein the first measurement is generated at a first sensing frequency based on the clock signal;

wherein the clock generator module is configured to dither the clock signal; and

wherein the determination module is configured to adjust a demodulation frequency based on the dithered clock signal to generate a second measurement of the capacitive sensing signal during a second time period at the first sensing frequency based on the dithered clock signal.

14. The processing system of claim 13 , wherein the determination module comprises demodulation circuitry configured to perform continuous-time demodulation of the capacitive sensing signal.

15. The processing system of claim 13 , wherein the clock generator module is configured to dither the clock signal at every sensing burst or every sensing half-period.

16. The processing system of claim 13 , wherein the demodulation frequency is adjusted by an amount that is inversely proportional to a value of the clock dithering.

17. The processing system of claim 13 , wherein the determination module is configured to adjust the demodulation frequency by adjusting at least one of: a hardware or firmware configuration of the processing system.

18. The processing system of claim 13 , wherein the determination module is configured to determine a clock dithering frequency, a value of the clock dithering, and the demodulation frequency adjustment by fetching a stored configuration indicating the clock dithering frequency, the value of the clock dithering, and the demodulation frequency adjustment.