IP Library Granted Patent US 10,180,855
Granted Patent B1
US 10,180,855 · App. 15/620,902 · Granted Jan 15, 2019

System and method for controlling idle state of operating system

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Quick Facts
Patent No.
US 10,180,855
App. No.
15/620,902
Granted
Jan 15, 2019
Kind
B1
Abstract

A system and method is provided for controlling an operating state of a virtual processor. An exemplary method includes determining a blocked state of a guest operating system, and, upon detecting the blocked state, determining a number of interrupt events during a first time period. If the number of interrupts is less than a first threshold or even zero during a first time period, the method includes protecting memory pages from execution by the virtual processor. Moreover, the method includes detecting, during a second time period, when the processor attempts to execute protected memory pages and unprotecting these protected memory page. Then, during a third time period, the method includes monitoring execution by the processor of the unprotected memory pages and maintaining the processor in an idle state based on the number of executed unprotected memory pages during the third time period.

Claims (44)

1. A method for controlling an operating state of a virtual processor, the method comprising:

determining if a guest system has entered a blocked state by executing an instruction halting the virtual processor until the next interrupt;

upon detecting the blocked state of the guest system, determining a number of interrupt events during a first time period;

if the number of interrupts is less than a first threshold during the first time period, protecting a plurality of memory pages from execution by the virtual processor;

detecting, during a second time period, when the virtual processor attempts to execute at least one of the plurality of protected memory pages;

unprotecting the at least one protected memory page that the virtual processor attempts to execute during the second time period;

monitoring execution by the virtual processor of the at least one unprotected memory page during a third time period; and

maintaining the virtual processor in an idle state based on the number of executed unprotected memory pages during the third time period.

2. The method of claim 1 , further comprising adding the at least one unprotected memory page to a list of executed memory pages.

3. The method of claim 2 , wherein the monitoring comprises determining whether a number of the executed unprotected memory pages on the list does not increase during the third time period.

4. The method of claim 3 , further comprising causing the virtual processor to leave the idle state and enter an active state when the number of the executed unprotected memory pages on the list increases during the third time period, wherein the active state comprises executing at least one thread by the virtual processor.

5. The method of claim 1 , wherein the virtual processor is for a virtual machine and the plurality of memory pages are guest pages stored in virtual memory of the virtual machine.

6. The method of claim 5 , wherein the protecting of the plurality of memory guest pages comprises setting an execute disable bit of at least one page table mapping the plurality of guest memory pages.

7. The method of claim 1 , wherein the guest system enters the blocked state upon at least one of a synchronous call to wait for a computing resource and an asynchronous hardware interrupt.

8. The method of claim 1 , wherein the determining that the guest system has entered the blocked state comprises detecting an HLT instruction for the virtual processor to enter the idle state.

9. The method of claim 1 , wherein the determining of the number of interrupt events executed by the virtual processor comprises determining that only timer device interrupts occur during the first time period.

10. The method of claim 9 , further comprising delaying the timer device interrupts when the virtual processor is in the idle state.

11. A system for controlling an operating state of a virtual machine, the system comprising:

an electronic memory configured to provide a virtual memory for storing a plurality of executable guest pages;

a hardware processor configured to execute a virtual processor for executing at least a portion of the plurality of executable guest pages; and

a virtual machine monitor configured to:

determine if a guest system of the virtual machine has entered a blocked state,

upon detecting the blocked state of the guest system, determine a number of interrupt events during a first time period,

if the number of interrupts is less than a first threshold during the first time period, protect the plurality of memory pages from execution by the virtual processor,

detect, during a second time period, when the virtual processor attempts to execute at least one of the plurality of protected memory pages,

unprotecting the at least one protected memory page that the virtual processor attempts to execute during the second time period,

monitor execution by the virtual processor of the at least one unprotected memory page during a third time period, and

maintain the virtual processor in an idle state based on the number of executed unprotected memory pages during the third time period.

12. The system of claim 11 , wherein the virtual machine monitor is further configured to add the at least one unprotected memory page to a list of executed memory pages.

13. The system of claim 12 , wherein the virtual machine monitor is further configured to determine whether a number of the executed unprotected memory pages on the list does not increase during the third time period.

14. The system of claim 13 , wherein the virtual machine monitor is further configured to cause the virtual processor to leave the idle state and enter an active state when the number of the executed unprotected memory pages on the list increases during the third time period.

15. The system of claim 11 , wherein the virtual machine monitor is configured to protect the plurality of memory guest pages by setting an execute disable bit of at least one page table mapped to the plurality of memory guest pages.

16. The system of claim 11 , wherein the guest system enters the blocked state upon at least one of a synchronous call to wait for a computing resource and an asynchronous hardware interrupt.

17. The system of claim 11 , wherein the virtual machine monitor is further configured to run the at least one thread and detect an HTL instruction for the virtual processor to enter the idle state.

18. The system of claim 11 , wherein the virtual machine monitor is further configured to determine the number of interrupt events executed by the virtual processor by determining that only timer device interrupts occur during the first time period.

19. The system of claim 9 , wherein the virtual machine monitor is further configured to delay the timer device interrupts when the processor is in the idle state.

20. A non-transitory computer readable medium comprising computer executable instructions for controlling an operating state of a virtual processor, including instructions for:

determining if a guest system has entered a blocked state;

upon detecting the blocked state of the guest system, determining a number of interrupt events during a first time period;

if the number of interrupts is less than a first threshold during the first time period, protecting a plurality of memory pages from execution by the virtual processor;

detecting, during a second time period, when the virtual processor attempts to execute at least one of the plurality of protected memory pages;

unprotecting the at least one protected memory page that the virtual processor attempts to execute during the second time period;

monitoring execution by the virtual processor of the at least one unprotected memory page during a third time period; and

maintaining the virtual processor in an idle state based on the number of executed unprotected memory pages during the third time period.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Jul 18, 2019
From: UBS AG, STAMFORD BRANCH, AS ADMINISTRATIVE AND COLLATERAL AGENT
To: COREL CORPORATION; CLEARSLIDE, INC.; PARALLELS INTERNATIONAL GMBH
Reel/Frame 049787/0073 →
RELEASE OF SECURITY INTEREST RECORDED AT : REEL 047973 FRAME 0797 Recorded Jul 17, 2019
From: UBS AG, STAMFORD BRANCH
To: PARALLELS INTERNATIONAL GMBH
Reel/Frame 049773/0590 →
SECURITY INTEREST Recorded Dec 21, 2018
From: PARALLELS INTERNATIONAL GMBH
To: UBS AG, STAMFORD BRANCH
Reel/Frame 047973/0797 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2017
From: KORYAKIN, ALEXEY; DOBROVOLSKIY, NIKOLAY; BELOUSSOV, SERGUEI M
To: PARALLELS INTERNATIONAL GMBH
Reel/Frame 042687/0611 →