Semiconductor device and method
A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.
1. A semiconductor device, comprising:
a first fin and a second fin disposed over a substrate;
a first epitaxial regrowth region over the first fin;
a second epitaxial regrowth region over the second fin, the second epitaxial regrowth region contacting the first epitaxial regrowth region;
a dielectric layer over the first epitaxial regrowth region and the second epitaxial regrowth region; and
a void region in the dielectric layer, the void region disposed under an upper-most surface of the first epitaxial regrowth region and under an upper-most surface of the second epitaxial regrowth region.
2. The semiconductor device of claim 1 , wherein the void region is disposed under contacting portions of the first epitaxial regrowth region and the second epitaxial regrowth region.
3. The semiconductor device of claim 2 , wherein contacting portions of the first epitaxial regrowth region and the second epitaxial regrowth region comprise a boundary of the void region.
4. The semiconductor device of claim 2 , wherein the void region adjoins contacting portions of the first epitaxial regrowth region and the second epitaxial regrowth region.
5. The semiconductor device of claim 1 , further comprising an isolation region interposed between the first fin and the second fin.
6. The semiconductor device of claim 5 , wherein the isolation region has an upper surface that is substantially planar, concave, or v-shaped.
7. The semiconductor device of claim 1 , wherein the dielectric layer encapsulates the first epitaxial regrowth region and the second epitaxial regrowth region.
8. The semiconductor device of claim 1 , further comprising:
a gate dielectric over the first fin and the second fin; and
a gate electrode over the gate dielectric.
9. A semiconductor device, comprising:
a plurality of fins disposed over a substrate;
a plurality of isolation structures interposed between respective pairs of the plurality of fins;
a plurality of epitaxial regrowth structures each disposed over respective ones of the plurality of fins, wherein each of the plurality of epitaxial regrowth structures adjoins adjacent ones of the plurality of epitaxial regrowth structures;
a dielectric layer encapsulating the plurality of epitaxial regrowth structures; and
a plurality of void regions in the dielectric layer, each of the plurality of void regions laterally interposed between respective pairs of the plurality of epitaxial regrowth structures.
10. The semiconductor device of claim 9 , wherein each of the plurality of void regions is disposed under contacting portions of respective adjacent pairs of the plurality of epitaxial regrowth structures.
11. The semiconductor device of claim 10 , wherein contacting portions of respective adjacent pairs of the plurality of epitaxial regrowth structures comprise a boundary of each of the plurality of void regions.
12. The semiconductor device of claim 10 , wherein each of the plurality of void regions adjoins contacting portions of respective adjacent pairs of the plurality of epitaxial regrowth structures.
13. The semiconductor device of claim 9 , wherein the plurality of isolation structures have upper surfaces that are substantially planar, concave, or v-shaped.
14. A method comprising:
forming a plurality of fin structures over a substrate;
forming a plurality of isolation structures laterally interposed between respective pairs of the plurality of fin structures;
etching an upper portion of the plurality of fin structures;
forming a plurality of epitaxial regrowth regions over respective ones of the plurality of fin structures, wherein each of the plurality of epitaxial regrowth regions adjoins adjacent ones of the plurality of epitaxial regrowth regions; and
depositing a dielectric layer over and on the plurality of epitaxial regrowth regions, wherein a plurality of void regions is formed in the dielectric layer, and each of the plurality of void regions is laterally interposed between respective pairs of the plurality of fin structures.
15. The method of claim 14 , wherein etching the upper portion of the plurality of fin structures further comprises etching the plurality of isolation structures.
16. The method of claim 14 , wherein the plurality of void regions are disposed under contacting portions of adjoining adjacent epitaxial regrowth regions.
17. The method of claim 16 , wherein contacting portions of adjoining adjacent epitaxial regrowth regions form a boundary of each of the plurality of void regions.
18. The method of claim 16 , wherein each of the plurality of void regions adjoins respective contacting portions of respective adjoining adjacent epitaxial regrowth regions.
19. The method of claim 14 , wherein the plurality of isolation structures have upper surfaces that are substantially planar, concave, or v-shaped.
20. The method of claim 14 , wherein the dielectric layer encapsulates the plurality of epitaxial regrowth regions.