IP Library Granted Patent US 9,893,068
Granted Patent B2
US 9,893,068 · App. 15/623,076 · Granted Feb 13, 2018

Method for manufacturing a semiconductor device

Inventor: Hiroyuki Hoshizaki (Hitachinaka, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L27/10808H01L27/10852H01L28/90
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Quick Facts
Patent No.
US 9,893,068
App. No.
15/623,076
Granted
Feb 13, 2018
Kind
B2
Abstract

To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a plurality of capacitors, and an isolation insulating film. The interlayer insulating film is located over the substrate. The capacitors are located in a plurality of recesses, respectively. The recesses each have an opening in the surface of the interlayer insulating film. The isolation insulating film lies in the interlayer insulating film. The isolation insulating films are located between recesses adjacent to each other in plan view. Further, the isolation insulating film is made of a material different from that of the interlayer insulating film.

Claims (11)

1. A method for manufacturing a semiconductor device comprising:

forming a first interlayer insulating film over a semiconductor substrate;

forming a conductive film on the first interlayer insulating film;

forming a first isolation insulating film on the conductive film;

selectively removing the conductive film and the first isolation insulating film to expose a part of the first interlayer insulating film and to form a first wiring covered with the first isolation insulating film and a second wiring covered with the first isolation insulating film;

forming a second interlayer insulating film on the first interlayer insulating film and the first isolation insulating film;

etching the first and the second interlayer insulating films by using the first isolation insulating film as a mask to form a trench between the first and the second wirings; and

forming a lower electrode, a capacitor insulating film and an upper electrode in the trench to form a capacitor.

2. The method of manufacturing the semiconductor device according to claim 1 , wherein a material of the first isolation insulating film is different from that of the first and the second interlayer insulating films.

3. The method of manufacturing the semiconductor device according to claim 1 , wherein an etch selectivity of the first and the second interlayer insulating films is large relative to the first isolation insulating film.

4. The method of manufacturing the semiconductor device according to claim 1 , wherein the first and the second wirings comprises a first and a second bit line, respectively.

Assignments (1)
CHANGE OF ADDRESS OF ASSIGNEE Recorded Jun 1, 2018
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 045984/0759 →
Priority Claims (1)
JP 2014-091299 · Apr 25, 2014 · national
Continuity (2)
Continuation 14694338 · Apr 23, 2015
Related Publication 20170287916A1 · Oct 5, 2017