Method of controlling wafer bow in a type III-V semiconductor device
A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
1. A method of forming a type III-V semiconductor device, the method comprising:
providing a type IV semiconductor substrate comprising a main surface;
forming a type III-V semiconductor channel region over the type IV semiconductor substrate, the type III-V semiconductor channel region comprising a two-dimensional carrier gas,
forming a type III-V semiconductor lattice transition region between the type IV semiconductor substrate and the type III-V semiconductor channel region, the type III-V semiconductor lattice transition region being configured to alleviate mechanical stress arising from lattice mismatch between the type IV semiconductor substrate and the type III-V semiconductor channel region;
forming a nucleation layer that comprises a metal nitride between the type IV semiconductor substrate and the type III-V semiconductor lattice transition region; and
controlling a process parameter for forming the nucleation layer so as to reduce a substrate bow of the type III-V semiconductor device wherein the process parameter for forming the nucleation layer comprises at least one of: an annealing and nitridation step for forming the nucleation layer, and an epitaxial deposition step for forming the nucleation layer, wherein forming the nucleation layer comprises forming a first low temperature layer and forming a second high temperature layer, wherein the annealing and nitridation step for forming the first low temperature layer as well as the epitaxial deposition step for forming the first low temperature layer are performed at a temperature of between 850° C. and 1200° C., and wherein the annealing and nitridation step for forming the second high temperature layer as well as the epitaxial deposition step for forming the second high temperature layer are performed at a temperature of above 1200° C.
2. The method of claim 1 , wherein controlling the process parameter for forming the nucleation layer comprises controlling the temperature of the annealing and nitridation step for forming the first low temperature layer.
3. The method of claim 1 , wherein controlling the process parameter for forming the nucleation layer comprises controlling the temperature of the epitaxial deposition step for forming the first low temperature layer.