Frequency estimation, correction and noise suppression for modems
View Patent ↗A frequency-shift keying (FSK) demodulator includes a digital phase-locked loop (DPLL) based frequency estimator to convert a phase signal to a frequency signal, a frequency offset estimator to estimate and track direct current (DC) component of the frequency signal, and an average filter communicatively coupled to the frequency offset estimator to perform an accumulate-and-dump operation to improve a symbol-level signal to noise ratio (SNR) of the frequency signal.
1. A frequency-shift keying (FSK) demodulator, comprising:
a digital phase-locked loop (DPLL) based frequency estimator that converts a phase signal to a frequency signal;
a frequency offset estimator communicatively coupled to the DPLL based frequency estimator, the frequency offset estimator that estimated and track direct current (DC) component of the frequency signal;
an average filter communicatively coupled to the frequency offset estimator, the average filter performing an accumulate-and-dump operation; and
a slicer communicatively coupled to the average filter that outputs demodulated bits.
2. The FSK demodulator of claim 1 , wherein the frequency offset estimator comprises one or more envelope detectors.
3. The FSK demodulator of claim 2 , wherein the one or more envelope detectors implement at least an acquisition mode and a tracking mode.
4. The FSK demodulator of claim 3 , wherein the acquisition mode is assigned a first weight and the tracking mode is assigned a second weight, wherein the first weight is initially set to be greater than the second weight, and where upon completion of synchronization, the first weight is reduced to be lower than the second weight.
5. The FSK demodulator of claim 1 , wherein the average filter comprises a first average filter and a second average filter separate from the first average filter.
6. The FSK demodulator of claim 5 , wherein the first average filter has a first accumulation length that corresponds to symbol duration of data being demodulated.
7. The FSK demodulator of claim 6 , wherein the second average filter has a second accumulation length that is shorter than the first accumulation length of the first average filter.
8. The FSK demodulator of claim 7 , wherein the second average filter operated on preambles and access addresses of packets received to complete synchronization, and wherein upon completion of synchronization, the first average filter performs data equalization and demodulation.
9. The FSK demodulator of claim 1 , wherein the DPLL based frequency estimator defines a transfer function that operates as a phase differentiator.
10. The FSK demodulator of claim 9 , wherein the transfer function implements flexible bandwidth in the DPLL based frequency estimator by adjusting a variable in the transfer function.
11. The FSK demodulator of claim 1 , wherein the FSK demodulator is a Bluetooth demodulator or a Bluetooth Low Energy (BLE) demodulator.
12. A frequency-shift keying (FSK) demodulator, comprising:
a digital phase-locked loop (DPLL) based frequency estimator that converts a phase signal to a frequency signal;
a frequency offset estimator communicatively coupled to the DPLL based frequency estimator, the frequency offset estimator comprising one or more envelope detectors that estimate and track direct current (DC) component of the frequency signal;
an average filter communicatively coupled to the frequency offset estimator, the average filter performing an accumulate-and-dump operation; and
a slicer communicatively coupled to the average filter that outputs demodulated bits.
13. The FSK demodulator of claim 12 , wherein the one or more envelope detectors comprise a positive envelope detector and a negative envelope detector, the positive envelope detector and negative envelope detector implementing at least an acquisition mode and a tracking mode.
14. The FSK demodulator of claim 13 , wherein the acquisition mode is assigned a first weight and the tracking mode is assigned a second weight, wherein the first weight is initially set to be greater than the second weight, and where upon completion of synchronization, the first weight is reduced to be lower than the second weight.
15. The FSK demodulator of claim 12 , wherein the average filter comprises a first average filter and a second average filter separate from the first average filter, wherein the first average filter has a first accumulation length that corresponds to symbol duration of data being demodulated, and wherein the second average filter has a second accumulation length that is shorter than the first accumulation length of the first average filter.
16. The FSK demodulator of claim 15 , wherein the second average filter operates on preambles and access addresses of packets received to complete synchronization, and wherein upon completion of synchronization, the first average filter performs data equalization and demodulation.
17. The FSK demodulator of claim 12 , wherein the DPLL based frequency estimator defines a transfer function that functions as a phase differentiator, and wherein the transfer function implements flexible bandwidth in the DPLL based frequency estimator by adjusting a variable in the transfer function.