Low cost, hardened single board computer for command and data handling
A radiation hardened single board computer (SBC) includes a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces.
1. A radiation hardened single board computer (SBC) comprising:
a processor;
static random-access memory (SRAM);
non-volatile memory;
a field programmable gate array (FPGA); and
board-level physical layer interfaces, wherein the SBC is configured to interface with one or more sensor boards not located within the SBC via the board-level physical layer interfaces, wherein each of the sensor boards comprises an FPGA comprising SRAM programming memory, and
wherein the FPGA of the SBC is configured to perform automated error detection and correction for errors found in the SRAM programming memory of each of the FPGAs of the one or more sensor boards.
2. The SBC of claim 1 , wherein the processor is an application specific integrated circuit.
3. The SBC of claim 1 , wherein the FPGA comprises physical layer support for:
high-speed serial interfaces;
Low-Voltage Differential Signaling (LVDS) interfaces;
an Inter-IC (I2C) interface;
SpaceWire; and
Joint Test Action Group (JTAG) interfaces.
4. The SBC of claim 1 , wherein the FPGA comprises a platform for custom hardware co-processing functions to reduce a load on a processor application-specific integrated circuit (ASIC).
5. The SBC of claim 1 , wherein the FPGA is configured to manage entire block reads and writes for flash memory.
6. The SBC of claim 1 , wherein the SBC is a payload processor for a set of instruments in Earth orbit applications.
7. The SBC of claim 1 , wherein the SBC consumes 6.6 W or less.
8. The SBC of claim 1 , wherein the SBC is configured to meet MicroTCA standards.
9. A field programmable gate array (FPGA) of a radiation hardened single board computer (SBC) configured to provide a platform for custom hardware co-processing functions to reduce a load on a processor application-specific integrated circuit (ASIC) of the SBC, the FPGA comprising:
physical layer support for interfaces,
wherein the SBC is configured to interface with a sensor board not located within the SBC, and
wherein the FPGA of the radiation hardened SBC is configured to perform automated error detection and correction for errors found in static random access memory (SRAM) configuration memory of an FPGA of the sensor board.
10. The FPGA of claim 9 , wherein the physical layer support comprises support for:
high-speed serial interfaces;
Low-Voltage Differential Signaling (LVDS) interfaces;
an Inter-IC (I2C) interface;
SpaceWire; and
Joint Test Action Group (JTAG) interfaces.
11. The FPGA of claim 9 , wherein the FPGA is configured to manage entire block reads and writes for flash memory.
12. The FPGA of claim 9 , wherein automated error detection and correction comprises:
detecting, at the FPGA, an error in the programming memory of the SRAM of the FPGA of the sensor board;
interrupting a processor of the sensor board; and
fixing, by the processor, the error in the programming memory of the SRAM of the FPGA of the sensor board.
13. The FPGA of claim 12 , wherein automated error detection and correction further comprises scrubbing, by the FPGA, the SRAM based FPGA of the sensor board by scanning the programming memory of the SRAM of the FPGA of the sensor board and comparing results of the scan with a set of local checksums.
14. The FPGA of claim 13 , wherein the FPGA is configured to perform the scrubbing autonomously without disturbing the processor.
15. The FPGA of claim 12 , wherein fixing the error comprises using a known good copy of the programming memory from a deep radiation hardened memory on the SBC.
16. A method of providing error detection and correction by a field programmable gate array (FPGA) and processor of a radiation hardened single board computer (SBC), the error detection and correction being for an instrument board not located within the SBC, the method comprising:
detecting, at the FPGA, an error in a configuration memory of the instrument board;
interrupting a processor of the instrument board, by the FPGA, when the error is detected; and
fixing, by the processor, the error in the configuration memory of the instrument board.
17. The method of claim 16 , further comprising scrubbing, by the FPGA, a SRAM based FPGA on the instrument board by scanning the configuration memory of the instrument board and comparing results of the scan with a set of local checksums.
18. The method of claim 17 , wherein the FPGA performs the scrubbing autonomously without disturbing the processor of the instrument board.
19. The method of claim 16 , wherein fixing the error comprises using a known good copy of the configuration memory from a deep radiation hardened memory on the SBC.
20. A radiation hardened single board computer (SBC) comprising:
a processor;
static random-access memory (SRAM);
non-volatile memory;
a field programmable gate array (FPGA); and
board-level physical layer interfaces, wherein the SBC is configured to interface with one or more sensor boards via the board-level physical layer interfaces,
wherein the FPGA is configured to perform automated error detection and correction for errors found in a plurality of SRAM programming memory of FPGAs of the sensor boards, and
wherein the SBC consumes 6.6 W or less.