Spur cancellation system for modems
A modem includes a modulator and a demodulator. The demodulator includes a direct current removing (DCR) circuit to transition between an acquisition mode, where the DCR circuit operates with a first loop gain; and a tracking mode, where the DCR circuit operates with a second loop gain. The second loop gain is smaller than the first loop gain, and the timing of the transition between the acquisition mode and tracking mode is programmable.
1. A demodulator, comprising:
a receiver; and
a direct current removing (DCR) circuit, the DCR circuit transitions between:
an acquisition mode, wherein the DCR circuit operates with a loop gain block having a first loop gain and first accumulation value to identify a plurality of harmonic spurs resulting from a 16 MHz clock frequency oscillator, including a spur at 2480 MHz coinciding with a center frequency of a Bluetooth low energy radio; and
a tracking mode, wherein the DCR circuit operates with the loop gain block having a second loop gain and second accumulation value,
wherein:
the second loop gain is smaller than the first loop gain;
each of the first loop gain and second loop gain is constrained to a power of 2 and implemented as bit shifts in a system of registers;
the second accumulation value is defined by the first accumulation value multiplied by the first loop gain, divided by the second loop gain;
a timing of the transition between the acquisition mode and tracking mode is programmable; and
the DCR circuit re-identifies the spurs whenever the receiver is cycled from an off power state to an on power state.
2. The demodulator of claim 1 , wherein the DCR circuit transitions to a holding mode to freeze a loop gain of the DCR circuit for data demodulation.
3. The demodulator of claim 2 , wherein the transition to the holding mode occurs upon completion of synchronization.
4. The demodulator of claim 1 , wherein the transition between the acquisition mode and the tracking mode is controlled by a hardware finite state machine.
5. The demodulator of claim 4 , wherein a spur estimate acquired in the acquisition mode is used as an initial value for the tracking mode.
6. The demodulator of claim 5 , wherein an accumulation value maintained by the DCR circuit operating in the acquisition mode is scaled when the DCR circuit transitions from the acquisition mode to the tracking mode.
7. The demodulator of claim 1 , wherein the demodulator is a frequency-shift keying (FSK) demodulator.
8. The demodulator of claim 1 , wherein the DCR circuit forms at least a part of a digital front end of the demodulator.
9. A demodulator, comprising:
a receiver; and
a direct current removing (DCR) circuit comprising a system of registers configured to bit shift a signal according to one of a plurality of loop gain values, the DCR circuit transitions among:
an acquisition mode, wherein the DCR circuit operates with a loop gain block having a first loop gain and first accumulation value to identify a plurality of harmonic spurs resulting from a 16 MHz clock frequency oscillator, including a spur at 2480 MHz coinciding with a center frequency of a Bluetooth low energy radio;
a tracking mode, wherein the DCR circuit operates with the loop gain block having a second loop gain and second accumulation value; and
a holding mode, wherein the DCR circuit freezes a loop gain of the DCR circuit for data demodulation,
wherein:
the second loop gain is smaller than the first loop gain;
the second accumulation value is defined by the first accumulation value multiplied by the first loop gain, divided by the second loop gain;
each of the first loop gain and second loop gain is constrained to a power of 2;
a timing of the transition between the acquisition mode and tracking mode is programmable;
the transition to the holding mode occurs upon completion of synchronization; and
the DCR circuit re-identifies the spurs, beginning with the frozen loop gain, whenever the receiver is cycled from an off power state to an on power state.
10. The demodulator of claim 9 , wherein the transition among the acquisition mode, the tracking mode, and the holding mode is controlled by a hardware finite state machine.
11. The demodulator of claim 9 , wherein a spur estimate acquired in the acquisition mode is used as an initial value for the tracking mode.
12. The demodulator of claim 11 , wherein an accumulation value maintained by the DCR circuit operating in the acquisition mode is scaled when the DCR circuit transitions from the acquisition mode to the tracking mode.
13. The demodulator of claim 9 , wherein the demodulator is a frequency-shift keying (FSK) demodulator.
14. The demodulator of claim 9 , wherein the DCR circuit forms at least a part of a digital front end of the demodulator.
15. A method for demodulating a signal, comprising:
placing a direct current removing (DCR) circuit into an acquisition mode having a first loop gain and a loop gain block maintains a first accumulation value;
setting an acquisition mode timer of no more than 4 microseconds;
identifying a spur in a plurality of harmonic spurs resulting from a 16 MHz clock frequency oscillator, the spur at 2480 MHz coinciding with a center frequency of a Bluetooth low energy radio;
converting a signal from a first clock domain defined by the clock frequency, to a second clock domain having a lower clock speed than the first clock domain via bit shift by a decimation filter;
placing the DCR circuit into a tracking mode having a second loop gain and the loop gain block maintains a second accumulation value based on at least one of the acquisition mode timer expiring or identifying the spur; and
re-identifying the spurs whenever a receiver is cycled from an off power state to an on power state,
wherein:
the second loop gain is smaller than the first loop gain;
the second accumulation value is defined by the first accumulation value multiplied by the first loop gain, divided by the second loop gain.
16. The method of claim 15 , further comprising placing the DCR circuit into a holding mode to freeze a loop gain of the DCR circuit for data demodulation.
17. The method of claim 16 , further comprising transitioning from the holding mode to one of the tracking mode or acquisition mode when a packet error ratio exceeds a threshold.
18. The method of claim 15 , wherein identifying when to place the DCR circuit into the tracking mode is controlled by a hardware finite state machine.
19. The method of claim 15 , further comprising acquiring a spur estimate in the acquisition mode as an initial value for the tracking mode.
20. The method of claim 19 , further comprising scaling an accumulation value identified in the acquisition mode prior to placing the DCR circuit into the tracking mode.