Digital-to-analog converter (DAC) with digital offsets
View Patent ↗Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.
1. A method, comprising:
determining a digital offset for application to a digital input to a digital-to-analog converter (DAC) that comprises a plurality of conversion elements, wherein each conversion element handles a particular bit in digital inputs to said DAC, said determining comprising:
determining when one or more conditions relating to digital inputs to said DAC are present, wherein said one or more conditions comprise signal backoff;
determining one or more effects of said one or more conditions on switching characteristics of one or more of said plurality of conversion elements; and
setting a value of said digital offset based on said determined one or more effects of said one or more conditions;
applying said digital offset to said digital input; and
applying, via said DAC, digital-to-analog conversion to said digital input with said digital offset.
2. The method of claim 1 , comprising selectively applying one or more adjustments to said digital offset for one or more particular digital input conditions.
3. The method of claim 1 , comprising dynamically determining said digital offset during handling of said digital input.
4. The method of claim 1 , comprising adaptively determining said digital offset based on said digital input and/or one or more conditions relating to said digital input.
5. The method of claim 1 , comprising determining said digital offset to modify one or more switching characteristics for at least one conversion element.
6. The method of claim 5 , wherein said modifying said one or more switching characteristics comprises eliminating one or more switching transitions for at least one conversion element.
7. The method of claim 1 , wherein switching characteristics comprise, for each conversion element, whether said conversion element switches or not for a particular digital input and/or one or more conditions related to said particular digital input.
8. A system comprising:
a processing circuit; and
a digital-to-analog converter (DAC) circuit configured for applying digital-to-analog conversions, said DAC circuit comprising a plurality of conversion elements with each conversion element configured to handle a particular bit in a digital input to said DAC circuit;
wherein:
said processing circuit is operable to determine a digital offset, for application to said digital input, wherein said processing circuit:
determines when one or more conditions relating to digital inputs to said DAC circuit are present, wherein said one or more conditions comprise signal backoff;
determines one or more effects of said one or more conditions on switching characteristics of one or more of said plurality of conversion elements; and
sets a value of said digital offset based on said determined one or more effects of one or more conditions; and
said DAC circuit is operable to:
apply said digital offset to a digital input to said DAC circuit; and
apply digital-to-analog conversion to said digital input with said digital offset.
9. The system of claim 8 , wherein said DAC circuit is operable to selectively apply one or more adjustments to said digital offset for one or more particular digital input conditions.
10. The system of claim 8 , wherein said processing circuit is operable to dynamically determine said digital offset during handling of said digital input.
11. The system of claim 8 , wherein said processing circuit is operable to adaptively determine said digital offset based on said digital input and/or one or more conditions relating to said digital input.
12. The system of claim 8 , wherein said processing circuit is operable to determine said digital offset to modify one or more switching characteristics for at least one conversion element.
13. The system of claim 12 , wherein said modifying of said one or more switching characteristics comprises eliminating one or more switching transitions for at least one conversion element.
14. The system of claim 8 , wherein switching characteristics comprise, for each conversion element, whether said conversion element switches or not for a particular digital input and/or one or more conditions related to said particular digital input.
15. The system of claim 8 , wherein said DAC circuit comprises a segmentation-based implementation, comprising a plurality of segments, with each segment comprising one or more conversion elements of said plurality of conversion elements.
16. The system of claim 15 , wherein said plurality of segments comprises:
a most significant bits (MSBs) segment; and
one or more least significant bits (LSBs) segments.
17. The system of claim 16 , wherein said plurality of segments comprises:
a lower least significant bits (LLSBs) segment;
a middle least significant bits (MLSBs) segment; and
an upper least significant bits (ULSBs) segment.
18. The system of claim 16 , wherein digital offset is determined based on one or more switching characteristics of only one or a portion of conversion elements in said MSBs segment.
19. A method, comprising:
determining a digital offset for application to a digital input to a digital-to-analog converter (DAC) that comprises a plurality of conversion elements, wherein each conversion element handles a particular bit in digital inputs to said DAC, said determining comprising:
determining said digital offset to modify one or more switching characteristics for at least one conversion element, wherein said modifying of said one or more switching characteristics comprises eliminating one or more switching transitions for said at least one conversion element;
determining when one or more conditions relating to digital inputs to said DAC are present;
determining one or more effects of said one or more conditions on switching characteristics of one or more of said plurality of conversion elements; and
setting a value of said digital offset based on said determined one or more effects of said one or more conditions; and
applying said digital offset to said digital input; and
applying, via said DAC, digital-to-analog conversion to said digital input with said digital offset.
20. The method of claim 19 , comprising selectively applying one or more adjustments to said digital offset for one or more particular digital input conditions.
21. The method of claim 19 , comprising dynamically determining said digital offset during handling of said digital input.
22. The method of claim 19 , comprising adaptively determining said digital offset based on said digital input and/or one or more conditions relating to said digital input.
23. The method of claim 19 , wherein switching characteristics comprise, for each conversion element, whether said conversion element switches or not for a particular digital input and/or one or more conditions related to said particular digital input.
24. A system comprising:
a processing circuit; and
a digital-to-analog converter (DAC) circuit configured for applying digital-to-analog conversions, said DAC circuit comprising a plurality of conversion elements with each conversion element configured to handle a particular bit in a digital input to said DAC circuit;
wherein:
said processing circuit is operable to determine a digital offset, for application to said digital input, wherein said processing circuit:
determines said digital offset to modify one or more switching characteristics for at least one conversion element, wherein said modifying of said one or more switching characteristics comprises eliminating one or more switching transitions for at least one conversion element;
determines when one or more conditions relating to digital inputs to said DAC circuit are present;
determines one or more effects of said one or more conditions on switching characteristics of one or more of said plurality of conversion elements; and
sets a value of said digital offset based on said determined one or more effects of one or more conditions; and
said DAC circuit is operable to:
apply said digital offset to a digital input to said DAC circuit; and
apply digital-to-analog conversion to said digital input with said digital offset.
25. The system of claim 24 , wherein said DAC circuit is operable to selectively apply one or more adjustments to said digital offset for one or more particular digital input conditions.
26. The system of claim 24 , wherein said processing circuit is operable to dynamically determine said digital offset during handling of said digital input.
27. The system of claim 24 , wherein said processing circuit is operable to adaptively determine said digital offset based on said digital input and/or one or more conditions relating to said digital input.
28. The system of claim 24 , wherein switching characteristics comprise, for each conversion element, whether said conversion element switches or not for a particular digital input and/or one or more conditions related to said particular digital input.
29. The system of claim 24 , wherein said DAC circuit comprises a segmentation-based implementation, comprising a plurality of segments, with each segment comprising one or more conversion elements of said plurality of conversion elements.
30. The system of claim 29 , wherein said plurality of segments comprises:
a most significant bits (MSBs) segment; and
one or more least significant bits (LSBs) segments.
31. The system of claim 30 , wherein said plurality of segments comprises:
a lower least significant bits (LLSBs) segment;
a middle least significant bits (MLSBs) segment; and
an upper least significant bits (ULSBs) segment.
32. The system of claim 30 , wherein digital offset is determined based on one or more switching characteristics of only one or a portion of conversion elements in said MSBs segment.