High voltage architecture for non-volatile memory

1. A method comprising:

applying, during an erase operation, a first high voltage signal (VPOS) to a common source line (CSL) and bit line (BL), wherein the CSL and BL are coupled to a non-volatile memory (NVM) cell of a first row of NVM cells of a memory device, wherein the CSL is shared among the NVM cell and one or more other NVM cells of the first row of NVM cells in a direction of the first row;

applying, during a program operation, a second high voltage signal (VNEG) to a word line (WL) and to a substrate line (SPW), wherein the WL and SPW are coupled to the NVM cell; and

applying a third high voltage signal to the CSL during the program operation, wherein the first high voltage signal is above a highest voltage of a power supply, wherein the second high voltage signal is below a lowest voltage of a ground supply of the memory device, and wherein the third high voltage signal is different than the second high voltage signal.

2. The method of claim 1 , further comprising applying a fourth high voltage signal to the word line during a read operation, wherein the fourth high voltage signal is above the highest voltage of the power supply.

3. The method of claim 1 , wherein the common source line is shared between a plurality of rows of NVM cells in a NVM sector.

4. The method of claim 1 , further comprising:

inhibiting, during the program operation, the NVM cell by applying a low voltage signal to the bit line, wherein the low voltage signal is within a voltage range of the power supply.

5. A system, comprising:

a plurality of non-volatile memory (NVM) cells in a sector, each of the plurality of NVM cells coupled to a common source line (CSL);

a local bit line (BL) coupled to at least one NVM cell of the plurality of NVM cells;

a word line (WL) coupled to the at least one NVM cell; and

a sector select circuit, coupled to a column of NVM cells in the sector, comprising at least one transistor disposed between the BL and a common line (CL), the sector select circuit to control a bit line voltage applied to the BL, the sector select circuit comprising:

a first N-channel metal oxide semiconductor field-effect transistor (nMOSFET) comprising a first gate, a first well, a first source, and first drain coupled to the local bit line;

a second nMOSFET comprising a second gate, a second well, a second drain, and second source coupled to the local bit line; and

a P-channel metal oxide semiconductor field-effect transistor (pMOSFET) comprising a third gate, a third well, a third drain, and third source coupled to the local bit line.

6. The system of claim 5 , wherein the sector select circuit further comprises an NMOS device disposed between the local bit line and a global bit line (GBL) to reduce leakage from one or more unselected sectors.

7. The system of claim 5 , further comprising:

a voltage control circuit that controls a plurality of high voltage (HV) signals for operation of at least one NVM cell while maintaining a safe operating area (SOA), wherein the plurality of high voltage signals are above a highest voltage of a power supply of or below a lowest voltage of a ground supply of a memory device, wherein the voltage control circuit applies;

a first high voltage signal (VPOS) to the common source line and local bit line during an erase operation to erase the NVM cell, wherein the first high voltage signal is above the highest voltage of the power supply; and

a second high voltage (HV) signal (VNEG) to the word line and to a substrate line (SPW) during a program operation to program the NVM cell, wherein the second high voltage signal is below the lowest voltage of the ground supply.

8. The system of claim 7 , wherein the safe operating area is a set of voltage differentials between different terminals of a transistor within which the transistor may be biased without damaging the transistor.

9. A method comprising:

performing a pre-programming operation on an NVM cell coupled to at least one transistor disposed between a bit line and a common line (CL), the at least one transistor comprising:

a first N-channel metal oxide semiconductor field-effect transistor (nMOSFET) comprising a first gate, a first well, a first source, and first drain coupled to a local bit line;

a second nMOSFET comprising a second gate, a second well, a second drain, and second source coupled to the local bit line; and

a P-channel metal oxide semiconductor field-effect transistor (pMOSFET) comprising a third gate, a third well, a third drain, and third source coupled to the local bit line;

wherein performing the pre-programming operation on the NVM cell comprises: applying a first high voltage signal (VPOS) to a first word line (WLS) coupled to the NVM cell;

applying a second high voltage signal (VNEG) to a second word line (WL) and to a substrate line (SPW) coupled to the NVM cell; and

applying a third high voltage signal (VNEG 3 ) to a common source line (CSL) coupled to the NVM cell, wherein the common source line is shared among NVM cells of a sector of NVM cells, and the first high voltage signal is above a highest voltage of a power supply of a memory device.

10. The method of claim 9 , further comprising:

erasing, during an erase operation, the NVM cell, the erasing comprising:

applying the first high voltage signal to the common source line and the bit line (BL);

applying the second high voltage signal to the first word line; and

applying the first high voltage signal to the substrate line.

11. The method of claim 10 , wherein pre-programing occurs prior to erasing.

12. The method of claim 9 , wherein the second high voltage signal is below a lowest voltage of a ground supply of the memory device.

13. The method of claim 9 , further comprising:

inhibiting, during a program operation, the NVM cell by applying a low voltage signal to the local bit line, wherein the low voltage signal is within a voltage range of the power supply.

14. The method of claim 9 , further comprising:

reading, during a read operation, the NVM cell by applying a fourth high voltage signal (VBST) to the second word line (WL), wherein the fourth high voltage signal is above the highest voltage of the power supply.

15. The method of claim 9 , wherein the NVM cell is a charge trapping memory cell.

16. The method of claim 9 , wherein the NVM cell is a silicon oxide nitride oxide silicon (SONOS) memory cell.

17. The method of claim 9 , wherein the common source line is shared between a plurality of rows of NVM cells and a plurality of columns of NVM cells of the sector.

18. The method of claim 9 , wherein the first high voltage signal, the second high voltage signal, and the third high voltage signal are applied for less than one millisecond.