Clock generator and processor system
View Patent ↗A clock generator outputs a processor clock that serves as an operation reference for a processor for use in a content protection system. The clock generator includes a direct digital synthesis and a random number generator. The direct digital synthesizer includes a phase accumulator and outputs the processor clock. The phase accumulator accumulates a setup value in synchronization with a reference clock. The random number generator generates random numbers. The setup value changes based on the random numbers.
1. A clock generator, comprising:
random number generator circuitry configured to generate random numbers;
direct digital synthesis circuitry configured to output a processor clock to processing circuitry for use in a content protection system; and
phase accumulator circuitry included in the direct digital synthesis circuitry, the phase accumulator circuitry being configured to
receive a setup value from the random number generator circuitry, the setup value changing based on the random numbers generated by the random number generator circuitry;
receive a reference clock; and
accumulate the received setup value in synchronization with the received reference clock, wherein
the setup value is composed of a plurality of bits,
a predetermined number of high order bits of the plurality of bits are set by the processing circuitry, the processing circuitry receiving the processor clock outputted from the direct digital synthesis circuitry and the processing circuitry using the processor clock as an operation reference, and
values of the predetermined number of the high order bits remain constant after being initialized.
2. The clock generator according to claim 1 , wherein the reference clock is a multi-phase reference clock.
3. A digital display comprising the clock generator according to claim 1 .
4. A digital AV receiver comprising the clock generator according to claim 1 .
5. The clock generator according to claim 1 , wherein
a frequency of the of the processor clock is randomized based on the setup value changing based on the random numbers.
6. A processor system, comprising:
processing circuitry for use in a content protection system; and
a clock generator that outputs, to the processing circuitry, a processor clock that serves as an operation reference for the processing circuitry, wherein
the clock generator comprises:
random number generator circuitry configured to generate random numbers;
direct digital synthesis circuitry configured to output the processor clock to the processing circuitry; and
phase accumulator circuitry included in the direct digital synthesis circuitry, the phase accumulator circuitry being configured to
receive a setup value from the random number generator circuitry, the setup value changing based on the random numbers generated by the random number generator circuitry;
receive a reference clock; and
accumulate the received setup value in synchronization with the received reference clock, wherein
the setup value is composed of a plurality of bits,
a predetermined number of high order bits of the plurality of bits are set by the processing circuitry, the processing circuitry receiving the processor clock outputted from the direct digital synthesis circuitry and the processing circuitry using the processor clock as the operation reference, and
values of the predetermined number of the high order bits remain constant after being initialized.
7. A method, comprising:
generating, using random number generator circuitry, random numbers;
outputting, using direct digital synthesis circuitry, a processor clock to processing circuitry for use in a content protection system; and
receiving, using phase accumulator circuitry included in the direct digital synthesis circuitry, a setup value from the random number generator circuitry, the setup value changing based on the random numbers generated by the random number generator circuitry;
receiving, using the phase accumulator circuitry, a reference clock; and
accumulating, using the phase accumulator circuitry, the received setup value in synchronization with the received reference clock, wherein
the setup value is composed of a plurality of bits,
a predetermined number of high order bits of the plurality of bits are set by the processing circuitry, the processing circuitry receiving the processor clock outputted from the direct digital synthesis circuitry and the processing circuitry using the processor clock as an operation reference, and
values of the predetermined number of the high order bits remain constant after being initialized.