Coarse pass and fine pass multi-level NVM programming

1. An electronic processing system, comprising:

a processor;

a multi-level NAND memory communicatively coupled to the processor, the multi-level NAND memory including:

a single-level cell (SLC) portion, and

a quad-level cell (QLC) portion;

a memory programmer communicatively coupled to the multi-level NAND memory to program the multi-level NAND memory, wherein the memory programmer is further to:

program the SLC portion in a first pass,

coarse program the QLC portion in the first pass, and

fine program the QLC portion in a second pass from data programmed in the SLC portion in the first pass; and

a page buffer communicatively coupled to the memory programmer to store a page of data, wherein the memory programmer is further to program the SLC portion from a first page of data stored in the page buffer at a same time as a second page of data is transferred to the page buffer.

2. The system of claim 1 , further comprising:

a page map translator communicatively coupled to the multi-level NAND memory to translate addresses between the SLC portion and the QLC portion.

3. The system of claim 2 , wherein the page map translator is integrated on a same die with the multi-level NAND memory.

4. The system of claim 1 , wherein the memory programmer is further to fine program the QLC portion from data stored in the SLC portion after a power interruption.

5. The system of claim 1 , wherein the data programmed in the QLC portion in the first pass is unverified.

6. A memory programmer apparatus, comprising:

a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass;

a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion; and

a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

7. The apparatus of claim 6 , further comprising:

a page map translator communicatively coupled to the first-level programmer, the coarse programmer, and the fine programmer to translate addresses between the first-level cell portion and the second-level cell portion.

8. The apparatus of claim 7 , wherein the page map translator is integrated on a same die with the multi-level memory.

9. The apparatus of claim 6 , wherein the fine programmer is further to fine program the second-level cell portion from data stored in the first-level cell portion after a power interruption.

10. The apparatus of claim 6 , wherein the data programmed in the second-level cell portion in the first pass is unverified.

11. The apparatus of claim 6 , further comprising:

a page buffer communicatively coupled to the first-level programmer to store a page of data, wherein the first-level programmer is further to program the first-level cell portion from a first page of data stored in the page buffer at a same time as a second page of data is transferred to the page buffer.

12. A method of programming a memory, comprising:

programming a first-level cell portion of a multi-level memory in a first pass;

coarse programming a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion; and

fine programming the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

13. The method of claim 12 , further comprising:

translating addresses between the first-level cell portion and the second-level cell portion.

14. The method of claim 13 , further comprising:

integrating address translation on a same die with the multi-level memory.

15. The method of claim 12 , further comprising:

fine programming the second-level cell portion from data stored in the first-level cell portion after a power interruption.

16. The method of claim 12 , wherein the data programmed in the second-level cell portion in the first pass is unverified.

17. The method of claim 12 , further comprising:

programming the first-level cell portion from a first page of data at a same time as a second page of data is transferred to the multi-level memory.

18. At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:

program a first-level cell portion of a multi-level memory in a first pass;

coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion; and

fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

19. The at least one computer readable medium of claim 18 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:

translate addresses between the first-level cell portion and the second-level cell portion.

20. The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:

integrate address translation on a same die with the multi-level memory.

21. The at least one computer readable medium of claim 18 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:

fine program the second-level cell portion from data stored in the first-level cell portion after a power interruption.

22. The at least one computer readable medium of claim 18 , wherein the data programmed in the second-level cell portion in the first pass is unverified.

23. The at least one computer readable medium of claim 18 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:

program the first-level cell portion from a first page of data at a same time as a second page of data is transferred to the multi-level memory.

24. A method of programming a memory, comprising:

programming a multi-level NAND memory including a single-level cell (SLC) portion and a quad-level cell (QLC) portion, comprising:

programming the SLC portion in a first pass from a first page of data stored in a page buffer at a same time as a second page of data is transferred to the page buffer;

coarse programming the QLC portion in the first pass; and

fine programming the QLC portion in a second pass from data programmed in the SLC portion in the first pass.

25. At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:

program a multi-level NAND memory including a single-level cell (SLC) portion and a quad-level cell (QLC) portion, wherein the computing device is to:

program the SLC portion in a first pass from a first page of data stored in a page buffer at a same time as a second page of data is transferred to the page buffer;

coarse program the QLC portion in the first pass; and

fine program the QLC portion in a second pass from data programmed in the SLC portion in the first pass.