Monolithic silicon bridge stack including a hybrid baseband die supporting processors and memory

1. A semiconductive device stack, comprising:

a baseband processor die including an active surface and a backside surface;

a recess disposed in the backside surface;

recess-seated device disposed in the recess;

a through-silicon via (TSV) in the baseband processor die that couples the active surface to the recess-seated die at the recess;

a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through a TSV at the backside surface;

a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die;

a redistribution layer (RDL) disposed on the active surface;

a ball-grid array disposed on the RDL;

a package substrate coupled to the ball-grid array; wherein the recess is a first recess, wherein the TSV is part of a first TSV group;

a subsequent recess disposed in the backside surface;

a subsequent recess-seated device disposed in the subsequent recess; and

a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess.

2. A semiconductive device stack, comprising:

a baseband processor die including an active surface and a backside surface;

a recess disposed in the backside surface;

recess-seated device disposed in the recess;

a through-silicon via (TSV) in the baseband processor die that couples the active surface to the recess-seated die at the recess wherein the recess is a first recess, wherein the TSV is part of a first TSV group;

a subsequent recess disposed in the backside surface;

a subsequent recess-seated device disposed in the subsequent recess; and

a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess.

3. The semiconductive device stack of claim 2 ,

wherein the first TSV group has a first height, the subsequent TSV group has a subsequent height, and wherein the first height and subsequent height are not equal.

4. The semiconductive device stack of claim 3 , further including:

a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through the TSV; and

wherein the TSV is part of a first TSV group, and wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die.

5. The semiconductive device stack of claim 3 , further including:

a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through the TSV;

Wherein the TSV is part of a first TSV group, and wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die; and

a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die.

6. A semiconductive device stack, comprising:

a baseband processor die including an active surface and a backside surface;

a recess disposed in the backside surface;

recess-seated device disposed in the recess;

a through-silicon via (TSV) in the baseband processor die that couples the active surface to the recess-seated die at the recess;

a processor die disposed on the baseband processor die backside surface, wherein the processor die is coupled to the baseband die through the TSV;

wherein the TSV is part of a first TSV group, and wherein the processor die also is coupled to a first lateral TSV group that is disposed in the baseband processor die; and

a die disposed in the recess, wherein the die is face-to-face mounted to the processor die.

7. The semiconductive device stack of claim 6 , further including

a memory die disposed on the processor die, wherein the processor die and the memory die communicate through a TSV in the processor die.

8. A process of forming a monolithic die stack, comprising:

forming a first recess in a baseband processor die backside surface, wherein the baseband processor die includes an active surface opposite the die backside;

seating a first recess-seated die in the first recess, wherein the first recess-seated die is coupled to the active surface by a through-silicon via (TSV);

mounting a processor die on the baseband die backside surface, wherein the processor die is coupled to the active surface by a first lateral TSV;

mounting a memory die on the processor die, wherein the memory die is coupled to the processor die by a first processor die TSV;

forming a subsequent recess in the baseband processor die backside surface, wherein the subsequent recess and the first recess are separately formed through the baseband processor die backside surface; and

seating a subsequent recess-seated die in the subsequent recess.

9. A computing system using a semiconductive device stack, comprising:

a baseband processor die including an active surface and a backside surface;

a first recess disposed in the backside surface;

first recess-seated device disposed in the first recess; and

a through-silicon via (TSV) in the baseband processor die that couples the baseband processor die at the active surface to the recess-seated die at the recess;

a redistribution layer (RDL) coupled to the active surface;

an electrical bump array coupled to the RDL;

a package substrate coupled to the electrical bump array; and

a physical shell coupled to the package substrate; wherein the recess is a first recess, wherein the TSV is part of a first TSV group, further including:

a subsequent recess disposed in the backside surface;

a subsequent recess-seated device disposed in the subsequent recess; and

a subsequent TSV group in the baseband processor die that couples the baseband processor die at the active surface to the subsequent recess-seated die at the subsequent recess.