TECHNIQUES TO SUPPORT MULITPLE INTERCONNECT PROTOCOLS FOR AN INTERCONNECT
Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.
1 . An apparatus to provide dynamic multi-protocol communication, the apparatus comprising:
an interconnect coupled with a device, the interconnect capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol;
interface logic coupled with the interconnect and a multi-protocol multiplexer, the interface logic at least partially implemented in hardware, to:
detect a message to communicate via the interconnect;
determine an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message; and
provide the message to the multi-protocol multiplexer, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.
2 . The apparatus of the claim 1 , the interface logic to:
determine the message is an input/output (I/O) message based on a lookup in an address map; and
determine the interconnect protocol is the non-coherent interconnect protocol based on the message.
3 . The apparatus of claim 2 , the interface logic to:
determine the I/O message is for the device coupled via the interconnect based on an address associated with the I/O message and the lookup in the address map; and
provide the I/O message to the multi-protocol multiplexer to communicate to the device.
4 . The apparatus of claim 1 , the interface logic to:
determine the message is a memory message for the device based on a lookup in an address map; and
determine the interconnect protocol is the memory interconnect protocol based on the message.
5 . The apparatus of claim 4 , the interface logic to:
determine the memory message is for the device coupled via the interconnect based on an address associated with the memory message and the lookup in the address map; and
provide the memory message to the multi-protocol multiplexer to communicate to the device.
6 . The apparatus of claim 1 , the interface logic to:
determine the message is a coherent message for the device based on performance of one or more cache coherency and memory access actions; and
determine the interconnect protocol is the coherent interconnect protocol based on the message.
7 . The apparatus of claim 1 , comprising:
the multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message based on resource availability of a protocol queue associated with the interconnect protocol at the device.
8 . The apparatus of claim 1 , the interface logic to dynamically switch between the plurality of interconnect protocols to cause communication of a plurality of messages via the interconnect, the multi-protocol multiplexer to communicate each of the plurality of messages in accordance with one of the interconnect protocols based on each of the plurality of messages.
9 . A non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry of an interface to:
detect a message to communicate via an interconnect coupled with a device, the interconnect capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol;
determine an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message; and
provide the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.
10 . The non-transitory computer-readable storage medium of claim 9 , comprising a plurality of instructions, that when executed, enable the processing circuitry to:
determine the message is an input/output (I/O) message based on a lookup in an address map; and
determine the interconnect protocol is the non-coherent interconnect protocol based on the message.
11 . The non-transitory computer-readable storage medium of claim 10 , comprising a plurality of instructions, that when executed, enable the processing circuitry to:
determine the I/O message is for the device coupled via the interconnect based on an address associated with the I/O message and the lookup in the address map; and
provide the I/O message to the multi-protocol multiplexer to communicate to the device.
12 . The non-transitory computer-readable storage medium of claim 9 , comprising a plurality of instructions, that when executed, enable the processing circuitry to:
determine the message is a memory message for the device based on a lookup in an address map; and
determine the interconnect protocol is the memory interconnect protocol based on the message.
13 . The non-transitory computer-readable storage medium of claim 12 , comprising a plurality of instructions, that when executed, enable the processing circuitry to:
determine the memory message is for the device coupled via the interconnect based on an address associated with the memory message and the lookup in the address map; and
provide the memory message to the multi-protocol multiplexer to communicate to the device.
14 . The non-transitory computer-readable storage medium of claim 9 , comprising a plurality of instructions, that when executed, enable the processing circuitry to:
determine the message is a coherent message for the device based on performance of one or more cache coherency and memory access actions; and
determine the interconnect protocol is the coherent interconnect protocol based on the message.
15 . The non-transitory computer-readable storage medium of claim 9 , the multi-protocol multiplexer to communicate the message based on resource availability of a protocol queue associated with the interconnect protocol at the device.
16 . The non-transitory computer-readable storage medium of claim 9 , comprising a plurality of instructions, that when executed, enable the processing circuitry to dynamically switch between the plurality of interconnect protocols to cause communication of a plurality of messages via the interconnect, the multi-protocol multiplexer to communicate each of the plurality of messages in accordance with one of the interconnect protocols based on each of the plurality of messages.
17 . A computer-implemented method to provide dynamic multi-protocol communication, comprising:
detecting a message to communicate via an interconnect coupled with a device, the interconnect capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol;
determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message; and
providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.
18 . The computer-implemented method of claim 17 , comprising:
determining the message is an input/output (I/O) message based on a lookup in an address map; and
determining the interconnect protocol is the non-coherent interconnect protocol based on the message.
19 . The computer-implemented method of claim 18 , comprising:
determining the I/O message is for the device coupled via the interconnect based on an address associated with the I/O message and the lookup in the address map; and
providing the I/O message to the multi-protocol multiplexer to communicate to the device.
20 . The computer-implemented method of claim 17 , comprising:
determining the message is a memory message for the device based on a lookup in an address map; and
determining the interconnect protocol is the memory interconnect protocol based on the message.
21 . The computer-implemented method of claim 20 , comprising:
determining the memory message is for the device coupled via the interconnect based on an address associated with the memory message and the lookup in the address map; and
providing the memory message to the multi-protocol multiplexer to communicate to the device.
22 . The computer-implemented method of claim 17 , comprising:
determining the message is a coherent message for the device based on performance of one or more cache coherency and memory access actions; and
determining the interconnect protocol is the coherent interconnect protocol based on the message.
23 . The computer-implemented method of claim 17 , comprising communicating, via the multi-protocol multiplexer, the message based on resource availability of a protocol queue associated with the interconnect protocol at the device.
24 . The computer-implemented method of claim 17 , comprising dynamically switching between the plurality of interconnect protocols to cause communication of a plurality of messages via the interconnect, the multi-protocol multiplexer to communicate each of the plurality of messages in accordance with one of the interconnect protocols based on each of the plurality of messages.