INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES
A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer.
1 .- 19 . (canceled)
20 . A method for outputting reliably predictable instruction sequences, comprising:
tracking fetches of instruction sequences from memory;
determining instruction sequences that exceed a threshold frequency of fetches to be a reliably predictable instruction sequence;
identifying a branch instruction preceding the instruction sequences that exceed the threshold;
storing the reliably predictable instruction sequence into a buffer; and
outputting the reliably predictable instruction sequence from the buffer into the pipeline of the processor, in response to a subsequent access of the branch instruction.
21 . The method of claim 20 , further comprising:
determining to evict the reliably predictable instruction sequence from the buffer, in response to an attempt to store another instructions sequence in the buffer when full.
22 . The method of claim 21 , wherein compare logic is used to evaluate the reliably predictable instruction sequence to determine whether said sequence should be evicted from the buffer, and wherein the reliably predictable instruction sequence is evicted from the buffer and stored in a second buffer as an alternative instruction sequence for retrieval therefrom upon a subsequent access to the branch instruction where a predicted outcome of the branch instruction is wrong.
23 . The method of claim 20 , wherein an address of a branch instruction is used to index the buffer.
24 . The method of claim 23 , wherein addresses of a plurality of following branches are used as tags to index the buffer.
25 . The method of claim 20 , wherein a plurality of branch prediction bits are used as tags to index the buffer.
26 . The method of claim 23 , wherein a hash of the address of the branch instruction is used to index the buffer.
27 . A processor pipeline for outputting reliably predictable instruction sequences, the processor pipeline comprising:
a buffer to store reliably predictable instruction sequences;
an instruction fetch that accesses a plurality of instructions from memory, the fetch means configured to track fetches of instruction sequences from memory, determine instruction sequences that exceed a threshold frequency of fetches to be a reliably predictable instruction sequence, identify a branch instruction preceding the instruction sequences that exceed the threshold, store the reliably predictable instruction sequence into the buffer, and output the reliably predictable instruction sequence from the buffer into the pipeline of the processor, in response to a subsequent access of the branch instruction.
28 . The processor pipeline of claim 27 , wherein the instruction fetch is further configured to determining to evict the reliably predictable instruction sequence from the buffer, in response to an attempt to store another instructions sequence in the buffer when full.
29 . The processor pipeline of claim 28 , wherein compare logic is used to evaluate the reliably predictable instruction sequence to determine whether said sequence should be evicted from the buffer, and wherein the reliably predictable instruction sequence is evicted from the buffer and stored in a second buffer as an alternative instruction sequence for retrieval therefrom upon a subsequent hit to the branch instruction where a predicted outcome of the branch instruction is wrong.
30 . The processor pipeline of claim 27 , wherein the buffer is configured to store the reliably predictable instruction sequence and is indexed to access the reliably predictable instruction sequence in at least two ways.
31 . The processor pipeline of claim 27 , wherein an address of a branch instruction is used to index the buffer.
32 . The processor pipeline of claim 31 , wherein addresses of a plurality of following branches are used as tags to index the buffer or a hash of the address of the branch instruction is used to index the buffer.
33 . The processor pipeline of claim 31 , wherein a plurality of branch prediction bits are used as tags to index the buffer.
34 . A computing system comprising:
a memory to store instructions; and
a processor, wherein the processor includes a processor pipeline configured to output reliably predictable instruction sequences, the processor pipeline including a buffer to store reliably predictable instruction sequences, an instruction fetch that accesses a plurality of instructions from memory, the instruction fetch configured to track fetches of instruction sequences from memory, determine instruction sequences that exceed a threshold frequency of fetches to be a reliably predictable instruction sequence, identify a branch instruction preceding the instruction sequences that exceed the threshold, store the reliably predictable instruction sequence into a buffer, and output the reliably predictable instruction sequence from the buffer into the pipeline of the processor, in response to a subsequent access of the branch instruction.
35 . The computing system of claim 34 , wherein the instruction fetch is further configured to determining to evict the reliably predictable instruction sequence from the buffer, in response to an attempt to store another instructions sequence in the buffer when full.
36 . The computing system of claim 35 , wherein compare logic is used to evaluate the reliably predictable instruction sequence to determine whether said sequence should be evicted from the buffer, and wherein the reliably predictable instruction sequence is evicted from the buffer and stored in a second buffer as an alternative instruction sequence for retrieval therefrom upon a subsequent hit to the branch instruction where a predicted outcome of the branch instruction is wrong.
37 . The computing system of claim 34 , wherein the buffer is configured to store the reliably predictable instruction sequence and is indexed to access the reliably predictable instruction sequence in at least two ways.
38 . The computing system of claim 34 , wherein an address of a branch instruction is used to index the buffer.
39 . The computing system of claim 38 , wherein addresses of a plurality of following branches are used as tags to index the buffer or a hash of the address of the branch instruction is used to index the buffer.
40 . The processor pipeline of claim 38 , wherein a plurality of branch prediction bits are used as tags to index the buffer.