IP Library Granted Patent US 10,678,443
Granted Patent B2
US 10,678,443 · App. 15/643,140 · Granted Jun 9, 2020

Method and system for high-density converged storage via memory bus

Inventors: Shu Li (Bothell, WA); Jianjian Huo (San Jose, CA)
Assignee: Alibaba Group Holding Limited
G06F3/0611G06F3/0619G06F3/0647G06F3/0656G06F3/0658G06F3/0685G06F11/1012G06F11/1076G06F12/0246G06F12/0804G06F12/10G06F2212/1024G06F2212/205G06F2212/281G06F2212/401G06F2212/7201H03M13/09H03M13/2906
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Quick Facts
Patent No.
US 10,678,443
App. No.
15/643,140
Granted
Jun 9, 2020
Kind
B2
Abstract

One embodiment facilitates a high-density converged storage system. During operation, the system receives, by a volatile memory of a storage device via a memory bus, data to be stored in a non-volatile memory of the same storage device. The system writes, by a controller of the storage device, the data directly to the non-volatile memory via the volatile memory, e.g., without using a serial bus protocol.

Claims (79)

1. A computer-implemented method for facilitating a high-density converged storage system, the method comprising:

receiving, by a volatile memory of a storage device via a memory bus directly from a central processing unit of a host, data to be stored in a non-volatile memory of the same storage device,

wherein a controller of the storage device is situated in a data path for the data between the volatile memory and the non-volatile memory, and

wherein the data path for the data to be stored comprises the memory bus;

transmitting, by the volatile memory to the controller of the storage device, the data for storage in a buffer of the controller; and

writing, by the controller of the storage device via the data path, the data to the non-volatile memory based on the data as received by the volatile memory via the memory bus,

wherein the volatile memory, the controller, and the non-volatile memory are co-located on the same storage device.

2. The method of claim 1 , further comprising:

mapping, by the volatile memory, a logical block address of the data to a physical block address of the non-volatile memory,

wherein writing the data to the non-volatile memory is based on the physical block address.

3. The method of claim 1 , further comprising:

storing the data in a buffer of the volatile memory,

wherein transmitting the data for storage in the buffer of the controller and writing the data to the non-volatile memory are in response to determining that the data in the buffer of the volatile memory is to be flushed from the volatile memory and written to the non-volatile memory.

4. The method of claim 1 , further comprising:

processing, by the controller, the data, which comprises:

encoding the data based on a cyclic redundancy check;

compressing the encoded data;

encrypting the compressed data

encoding the encrypted data based on an error correction code (ECC); and

adjusting a format of the ECC-encoded data.

5. The method of claim 4 , wherein while processing the data, the method further comprises:

storing the data in a buffer of the controller based on a predetermined condition.

6. The method of claim 1 , wherein the data is received by the volatile memory via one or more of:

a memory channel switch;

a switch; and

a multiplexing device.

7. The method of claim 1 , wherein the high-density converged storage system includes the storage device and one or more other storage devices, and

wherein a respective storage device includes a volatile memory, a controller, and a non-volatile memory.

8. The method of claim 1 , wherein writing the data to the non-volatile memory is in response to determining, by a power-detecting circuit of the storage device, a loss in power.

9. The method of claim 1 , further comprising:

receiving, by the volatile memory of the storage device via the memory bus directly from the central processing unit of the host, a request to read the data previously written directly to the non-volatile memory via the volatile memory;

retrieving, by the controller of the storage device, the data from the non-volatile memory of the same storage device; and

returning the retrieved data via the volatile memory.

10. The method of claim 9 , further comprising:

obtaining, by a flash translation layer module of the volatile memory, a mapping of a logical block address of the data to a physical block address of the data in the non-volatile memory,

wherein retrieving the data from the non-volatile memory is based on the physical block address, and

wherein the retrieved data is returned to a processor associated with the storage device.

11. The method of claim 9 , further comprising:

processing, by the controller, the retrieved data, which comprises:

adjusting a format of the retrieved data;

decoding the adjusted data based on an error correction code (ECC);

decrypting the ECC-decoded data;

decompressing the decrypted data; and

decoding the decompressed data based on a cyclic redundancy check.

12. The method of claim 11 , wherein while processing the retrieved data, the method further comprises:

storing the retrieved data in a first buffer of the controller based on a predetermined condition.

13. The method of claim 9 , wherein retrieving the data from the non-volatile memory is in response to determining, by the volatile memory, that the data is not stored in the volatile memory, and wherein the method further comprises:

in response to determining that the data is stored in the volatile memory, retrieving, by the volatile memory, the data from the volatile memory.

14. A computer system for facilitating a high-density converged storage system, the system comprising:

a processor; and

a memory coupled to the processor and storing instructions, which when executed by the processor cause the processor to perform a method, the method comprising:

receiving, by a volatile memory of a storage device via a memory bus directly from a central processing unit of a host, data to be stored in a non-volatile memory of the same storage device,

wherein a controller of the storage device is situated in a data path for the data between the volatile memory and the non-volatile memory, and

wherein the data path for the data to be stored comprises the memory bus;

transmitting, by the volatile memory to the controller of the storage device, the data for storage in a buffer of the controller; and

writing, by the controller of the storage device via the data path, the data to the non-volatile memory based on the data as received by the volatile memory via the memory bus,

wherein the volatile memory, the controller, and the non-volatile memory are co-located on the same storage device.

15. The computer system of claim 14 , wherein the method further comprises:

mapping, by the volatile memory, a logical block address of the data to a physical block address of the non-volatile memory,

wherein writing the data to the non-volatile memory is based on the physical block address.

16. The computer system of claim 14 , wherein the method further comprises:

storing the data in a buffer of the volatile memory,

wherein transmitting the data for storage in the buffer of the controller and writing the data to the non-volatile memory are in response to determining that the data in the buffer of the volatile memory is to be flushed from the volatile memory and written to the non-volatile memory.

17. The computer system of claim 14 , wherein the method further comprises:

processing, by the controller, the data, which comprises:

encoding the data based on a cyclic redundancy check;

compressing the encoded data;

encrypting the compressed data

encoding the encrypted data based on an error correction code (ECC); and

adjusting a format of the ECC-encoded data; and

wherein while processing the data, the method further comprises:

storing the data in a buffer of the controller based on a predetermined condition.

18. The computer system of claim 14 , wherein the data is received by the volatile memory via one or more of:

a memory channel switch;

a switch; and

a multiplexing device.

19. The computer system of claim 14 , wherein the high-density converged storage system includes the storage device and one or more other storage devices, and

wherein a respective storage device includes a volatile memory, a controller, and a non-volatile memory.

20. The computer system of claim 14 , wherein writing the data to the non-volatile memory is in response to determining, by a power-detecting circuit of the storage device, a loss in power.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2026
From: ALIBABA GROUP HOLDING LIMITED
To: CLOUD INTELLIGENCE ASSETS HOLDING (SINGAPORE) PRIVATE LIMITED
Reel/Frame 075499/0384 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2017
From: LI, SHU; HUO, JIANJIAN
To: ALIBABA GROUP HOLDING LIMITED
Reel/Frame 042993/0580 →
Continuity (1)
Related Publication 20190012094A1 · Jan 10, 2019