METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes preparing a lead frame that includes a die pad including a first plane and a second plane located on an opposite side of the first plane, and a plurality of leads arranged next to the die pad, mounting a semiconductor chip including a surface, a plurality of electrodes formed over the surface, and a reverse side located on an opposite side of the surface over a chip mounting area of the first plane of the die pad, electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling other parts of the electrodes and the die pad through a second wire after the mounting the semiconductor chip, and after the electrically coupling, sealing the semiconductor chip, the first wires, and the second wire with a resin.
1 . A method for manufacturing a semiconductor device, the method comprising:
preparing a lead frame that comprises a die pad including a first plane and a second plane located on an opposite side of the first plane, and a plurality of leads arranged next to the die pad;
mounting a semiconductor chip including a surface, a plurality of electrodes formed over the surface, and a reverse side located on an opposite side of the surface over a chip mounting area of the first plane of the die pad;
electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling other parts of the electrodes and the die pad through a second wire after the mounting the semiconductor chip; and
after the electrically coupling, sealing the semiconductor chip, the first wires, and the second wire with a resin such that a part of each of the leads and the second plane of the die pad is configured to be exposed after the electrically coupling,
wherein an area of the first plane of the die pad is larger than an area of the reverse side of the semiconductor chip,
wherein the first plane of the die pad includes the chip mounting area, a first bonding area that is located between the chip mounting area and the leads and to which the second wire is bonded, a first hollow part arrangement area that is located between the first bonding area and the chip mounting area and in which a plurality of holes are formed, and a second hollow part arrangement area that is arranged between the first bonding area and a peripheral part of the die pad and in which the plurality of holes are formed,
wherein, over the second plane of the die pad, a stepped part that ranges to a side face of the die pad and a groove part that is arranged between a central part and the stepped part of the second plane of the die pad are provided,
wherein the first and second hollow part arrangement areas, and the first bonding area are arranged between the groove and the chip mounting area,
wherein the plurality of holes are formed in each of the first and the second hollow part arrangement areas, respectively, and the second wire is bonded to an area surrounded by the holes, and
wherein, in a cross sectional view, each of the plurality of holes does not penetrate the die pad.
2 . The method for manufacturing the semiconductor device according to claim 1 , wherein a surface roughness of the first plane in the chip mounting area, the first bonding area, and the first hollow part arrangement area is coarser than a surface roughness of the second plane.
3 . The method for manufacturing the semiconductor device according to claim 2 , wherein a depth of the groove part is deeper than a depth of the stepped part in the cross sectional view.
4 . The method for manufacturing the semiconductor device according to claim 1 , wherein the holes are formed in the first hollow part arrangement area and an arrangement space of adjacent holes among the holes is less than or equal to twice an opening size of each of the holes.
5 . The method for manufacturing the semiconductor device according to claim 1 , wherein, expressing a surface roughness of the first plane as a ratio (Sr) of a surface area of the roughened surface to a unit area of a flat surface, Sr is 1.2 or more.
6 . A semiconductor device, comprising:
a lead frame that comprises a die pad including a first plane and a second plane located on an opposite side of the first plane, and a plurality of leads arranged next to the die pad;
a semiconductor chip including a surface, a plurality of electrodes formed over the surface, and a reverse side located on an opposite side of the surface over a chip mounting area of the first plane of the die pad;
a plurality of first wires electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires;
a plurality of second wires electrically coupling other parts of the electrodes and the die pad through a second wire; and
a resin sealing the semiconductor chip, the first wires, and the second wire so that a part of each of the leads and the second plane of the die pad is configured to be exposed,
wherein an area of the first plane of the die pad is larger than an area of the reverse side of the semiconductor chip,
wherein the first plane of the die pad includes the chip mounting area, a first bonding area that is located between the chip mounting area and the leads and to which the second wire is bonded, a first hollow part arrangement area that is located between the first bonding area and the chip mounting area and in which a plurality of holes are formed, and a second hollow part arrangement area that is arranged between the first bonding area and a peripheral part of the die pad and in which the plurality of holes are formed,
wherein, over the second plane of the die pad, a stepped part that ranges to a side face of the die pad and a groove part that is arranged between a central part and the stepped part of the second plane of the die pad are provided,
wherein the first and second hollow part arrangement areas, and the first bonding area are arranged between the groove and the chip mounting area,
wherein the plurality of holes are formed in each of the first and the second hollow part arrangement areas, respectively, and the second wire is bonded to an area surrounded by the holes, and
wherein, in a cross sectional view, each of the plurality of holes does not penetrate the die pad.
7 . A semiconductor device according to claim 6 , wherein a surface roughness of the first plane in the chip mounting area, the first bonding area, and the first hollow part arrangement area is coarser than a surface roughness of the second plane.
8 . A semiconductor device according to claim 7 , wherein a depth of the groove part is deeper than a depth of the stepped part in the cross sectional view.
9 . A semiconductor device according to claim 6 , wherein the plurality of holes are formed in the first hollow part arrangement area and an arrangement space of adjacent holes among the holes is less than or equal to twice an opening size of each of the holes.
10 . A semiconductor device according to claim 6 , wherein, expressing a surface roughness of the first plane as a ratio (Sr) of a surface area of the roughened surface to a unit area of a flat surface, Sr is 1.2 or more.
11 . A semiconductor device, comprising:
a lead frame that comprises a die pad including a first plane and a second plane located on an opposite side of the first plane, and a plurality of leads arranged next to the die pad;
a semiconductor chip including a surface, a plurality of electrodes formed over the surface, and a reverse side located on an opposite side of the surface over a chip mounting area of the first plane of the die pad;
a plurality of first wires electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires;
a plurality of second wires electrically coupling other parts of the electrodes and the die pad through a second wire; and
a resin sealing the semiconductor chip, the first wires, and the second wire such that a part of each of the leads and the second plane of the die pad is configured to be exposed.