Semiconductor device including a vertical one-time programmable fuse that includes a conductive layer and a resistive material and a method of making the same

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first insulating layer over the substrate;

forming a first opening through the first insulating layer;

forming a first conductive layer along a sidewall of the first opening; and

depositing a resistive material within the first opening over the first conductive layer, wherein:

the resistive material has a resistivity 10 times or greater than the first conductive layer, and

the first conductive layer and resistive material form a vertical one-time-programmable (OTP) fuse with electrically conductive properties associated with the fuse along the sidewall of the first opening.

2. The method of claim 1 , wherein the first conductive layer includes silicide material.

3. The method of claim 1 , wherein the resistive material includes polysilicon.

4. The method of claim 1 , further including forming a second conductive layer over the vertical OTP fuse.

5. The method of claim 4 , further including:

forming a second insulating layer over the substrate prior to forming the first insulating layer;

forming a second opening through the second insulating layer;

depositing a conductive material in the second opening; and

forming a third conductive layer over the second insulating layer and conductive material, wherein the vertical OTP fuse is disposed between the second conductive layer and third conductive layer.

6. A method of making a vertical one-time-programmable (OTP) fuse, comprising:

forming a first doped region within a well region, wherein the first doped region and the well region have opposite conductivity types;

forming a first insulating layer over the first doped region with a first opening through the first insulating;

forming a conductive layer along a sidewall of the first opening, wherein the conductive layer is coupled to the first doped region; and

depositing a resistive material within the first opening over the conductive layer to form a first vertical OTP fuse.

7. The method of claim 6 , wherein the conductive layer directly contacts the first doped region.

8. The method of claim 6 , wherein forming the first doped region within the well region is performed to form a diode including the first doped and well regions.

9. The method of claim 6 , wherein forming the first doped region within the well region is performed to form parts of a first transistor.

10. The method of claim 6 , wherein the first transistor is a PNP bipolar junction transistor.

11. The method of claim 10 , further comprising forming an isolation region extending through the well region, wherein :

forming the doped region within the well region includes forming a second doped region within the well region, wherein the second doped region has an opposite conductivity type as compared to the well region,

the first transistor includes the first doped region and a first portion of the well region, and a second transistor includes the second doped region and a second portion of the well region,

forming the first insulating layer includes forming the first insulating layer over the second doped region with a second opening through the first insulating layer,

forming the conductive layer includes forming the conductive layer along a sidewall of the second opening, wherein the conductive layer within the second opening is coupled to the second doped region,

depositing the resistive material includes depositing the resistive material within the second opening over the conductive layer to form a second vertical OTP fuse within the second opening of the first insulating layer, and

from a top view, the first transistor and the first vertical OTP are along one side of the isolation region, and the second transistor and the second vertical OTP fuse are along an opposite side of the isolation region.

12. The method of claim 6 , further including forming a second vertical OTP fuse at a different elevation as compared to the first vertical OTP fuse, wherein the second vertical OTP fuse is for redundancy.

13. A semiconductor device, comprising:

a substrate;

a first insulating layer over the substrate with a first opening through the first insulating layer; and

a first vertical one-time programmable (OTP) fuse within the first opening and including:

a first conductive layer along a sidewall of the first opening; and

a resistive material within the first opening over the first conductive layer, wherein the resistive material has a resistivity 10 times or greater than the first conductive layer.

14. The semiconductor device of claim 13 , wherein the first conductive layer includes silicide material.

15. The semiconductor device of claim 13 , further including:

a second conductive layer under the first vertical OTP fuse:

a second insulating layer over the substrate with a second opening through the second insulating layer;

a conductive material in the second opening; and

a third conductive layer over the second insulating layer and conductive material, wherein the first vertical OTP fuse is disposed between the second conductive layer and third conductive layer.

16. The semiconductor device of claim 13 , further including a second vertical OTP fuse lying at a different elevation as compared to the first vertical OTP fuse, wherein the second vertical OTP is for redundancy.

17. The semiconductor device of claim 13 , further including a plurality of vertical OTP fuses arranged in an array across the substrate.

18. The semiconductor device of claim 14 , further comprising:

a second conductive layer overlying the first vertical OTP fuse;

a second insulating layer over the substrate with a second opening through the second insulating layer;

a second vertical OTP fuse within the second opening: and an electronic component including a first terminal and a second terminal,

wherein the first OTP fuse, the second OTP fuse, and the first terminal of the electronic component are coupled to one another at a node, and the second terminal of the electronic component is coupled to another part of the electronic device.

19. A semiconductor device, comprising:

a substrate;

a first insulating layer formed over the substrate with a first opening through the first insulating layer, wherein the first opening has a bottom; and

a programmed vertical one-time-programmable (OTP) fuse within the first opening and including:

a first conductive layer spaced apart from the bottom of the first opening; and

a resistive fill material remaining within the first opening.

20. The semiconductor device of claim 19 , wherein the resistive fill material lies at a center of the programmed vertical OTP fuse.