IP Library Granted Patent US 10,347,656
Granted Patent B2
US 10,347,656 · App. 15/644,613 · Granted Jul 9, 2019

Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit

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Quick Facts
Patent No.
US 10,347,656
App. No.
15/644,613
Granted
Jul 9, 2019
Kind
B2
Abstract

A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.

Claims (38)

1. A semiconductor device, comprising:

a substrate including a semiconductor wafer, a buried oxide layer over the semiconductor wafer, and a semiconductor material over the buried oxide layer;

an oxide along a sidewall of the semiconductor material;

an epitaxial layer within an opening of the substrate that extends through the semiconductor material and the buried oxide layer, wherein the epitaxial layer overlies the semiconductor wafer;

a first vertical power semiconductor device including a portion of the epitaxial layer;

a first control circuit in the semiconductor material of the substrate to control the first vertical power semiconductor device, wherein the first control circuit is spaced apart from the epitaxial layer; and

a first isolation trench between the first vertical power semiconductor device and the first control circuit, and between the oxide and the epitaxial layer.

2. The semiconductor device of claim 1 , further including a second isolation trench in the semiconductor material to isolate the first control circuit from a second control circuit.

3. The semiconductor device of claim 1 , wherein the buried oxide layer extends under the first control circuit.

4. The semiconductor device of claim 3 , further including a second trench along a bottom surface of the substrate opposite a top surface of the substrate and extending through the semiconductor wafer to the buried oxide layer.

5. The semiconductor device of claim 4 , wherein the second trench surrounds the first vertical power semiconductor device.

6. The semiconductor device of claim 4 , further including a second power semiconductor device in the substrate, wherein the second trench isolates the first vertical power semiconductor device from the second power semiconductor device.

7. The semiconductor device of claim 4 , further comprising an insulating layer within the second trench, wherein the second trench separates the semiconductor wafer into a control portion associated with the first control circuit and a power semiconductor device portion associated with the first vertical power semiconductor device.

8. The semiconductor device of claim 7 , further comprising a drain contact that contacts the power semiconductor device portion of the semiconductor wafer.

9. The semiconductor device of claim 1 , wherein a surface of the semiconductor material is coplanar with a surface of the epitaxial layer.

10. A monolithic semiconductor device, comprising:

a substrate including a semiconductor material along a top surface of the substrate, a semiconductor wafer along a bottom surface of the substrate, and a buried oxide layer between the semiconductor wafer and the semiconductor material;

an oxide along a sidewall of the semiconductor material and the buried oxide layer;

an epitaxial layer spaced apart from the semiconductor material and the buried oxide layer of the substrate;

a power semiconductor device including a portion within the epitaxial layer;

a first control circuit within the semiconductor material; and

a first isolation trench between the epitaxial layer and the semiconductor material of the substrate.

11. The monolithic semiconductor device of claim 10 , further including a second isolation trench in the semiconductor wafer to isolate the first control circuit from a second control circuit.

12. The monolithic semiconductor device of claim 10 , further including an interconnect structure over the power semiconductor device and first control circuit.

13. The monolithic semiconductor device of claim 10 , wherein the substrate is a silicon-on-insulator substrate.

14. The monolithic semiconductor device of claim 10 , wherein a surface of the semiconductor material is coplanar with a surface of the epitaxial layer.

15. The monolithic semiconductor device of claim 10 , wherein the epitaxial layer is disposed within an opening of the semiconductor material.

16. The monolithic semiconductor device of claim 10 , wherein the power semiconductor device is a vertical power semiconductor device.

17. The monolithic semiconductor device of claim 16 , further comprising a gate electrode of the power semiconductor device, wherein the gate electrode is disposed within a gate trench that extends into the epitaxial layer.

18. The monolithic semiconductor device of claim 10 , wherein the first control circuit is configured to sense a voltage of the power semiconductor device.

19. The monolithic semiconductor device of claim 10 , wherein the buried oxide layer is disposed between the first control circuit and the semiconductor wafer.

20. A semiconductor device, comprising:

a substrate including a semiconductor material along a top surface of the substrate and a semiconductor wafer along a bottom surface of the substrate;

an epitaxial layer spaced apart from the semiconductor material;

a power semiconductor device including a portion within the epitaxial layer;

a control circuit within the semiconductor material;

a first isolation trench between the epitaxial layer and the semiconductor material of the substrate; and

a second isolation trench along a bottom surface of the substrate opposite the top surface and extending through the semiconductor wafer, wherein the second isolation trench includes an insulating layer and separates the semiconductor wafer into a control portion associated with the control circuit and a power semiconductor device portion associated with the power semiconductor device.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 046530, FRAME 0460 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064075/0001 →
PATENT SECURITY AGREEMENT Recorded Jul 11, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046530/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2017
From: HALL, JEFFERSON W.; GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 043020/0504 →