Access devices to correlated electron switch
Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.
1. A method comprising:
forming one or more first layers comprising a metal oxide to construct a correlated electron switch (CES); and
forming one or more second layers between a third layer and the one or more first layers to provide a first access device to the CES, wherein the third layer comprises a first metal layer to provide a first terminal of the CES.
2. The method of claim 1 , and further comprising forming one or more fourth layers between a fifth layer and the one or more first layers to provide a second access device to the CES, wherein the fifth layer comprises a second metal layer to provide a second terminal of the CES.
3. The method of claim 1 , wherein the third layer is formed over the one or more second layers.
4. The method of claim 1 , wherein the one or more second layers is n-type doped or p-type doped.
5. The method of claim 1 , wherein the one or more second layers comprises a polysilicon.
6. The method of claim 1 , wherein the one or more second layers comprises a metal oxide.
7. A device comprising:
one or more first layers a correlated electron switch (CES), at least one of the first layers comprising a first metallic oxide in an intrinsic state and at least one of the first layers comprising a second metallic oxide in a doped state;
one or more terminals; and
one or more second layers formed between a first terminal of the one or more terminals and the one or more first layers to form a first access device to the CES.
8. The device of claim 7 , wherein the CES is responsive to application of a first voltage across the one or more first metallic layers while maintaining a first current through the one or more first layers to place the CES in a high impedance or insulative state;
wherein the CES is responsive to application of a second voltage across the one or more first layers while maintaining a second current through the one or more first layers to place the memory state of the CES in a low impedance or conductive state; and
wherein an impedance state of the CES is detectable based, at least in part, on a measured current through the access device in response to application of a third voltage across the one or more first layers.
9. The device of claim 7 , wherein the device comprises a correlated electron random access memory (CeRAM) element in a crosspoint memory array.
10. The device of claim 7 , wherein the one or more second layers comprises zinc oxide doped with bismuth.
11. The device of claim 4 , wherein the first access device comprises a P/N junction diode, a Schottky barrier diode, a metal-insulator-metal (MIM) diode, a tunnel diode or a varistor, or a combination thereof.
12. The device of claim 7 , wherein the one or more first layers and the one or more second layers are formed from a correlated electron material (CEM), and wherein the second metallic oxide is p-type doped.
13. The device of claim 12 , wherein the one or more second layers comprise the CEM in an intrinsic state.
14. The device of claim 12 , wherein at least one of the one or more second layers are n-type doped.
15. The device of claim 7 , and further comprising one or more third layers formed between a second terminal of the one or more terminals and the one or more first layers to form a second access device to the CES.
16. The device of claim 15 , wherein at least one of the one or more second layers is n-type doped and wherein at least one of the one or more third layers comprises a correlated electron material (CEM) in an intrinsic state.
17. The device of claim 15 , wherein the one or more first layers are separated from the one or more second layers by a first metallic layer, and wherein the one or more first layers are separated from the one or more third layers by a second metallic layer.
18. The device of claim 15 , and wherein at least one of the one or more second layers and at least one of the one or more third layers comprise a correlated electron material (CEM) in an intrinsic state.
19. The device of claim 15 , wherein at least one of the one or more second layers and at least one of the one or more third layers are n-type doped.
20. The device of claim 15 , wherein at least one of the one or more second and at least one of the one or more third layers are n-type doped.