NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS
Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.
1 - 10 . (canceled)
11 . An integrated circuit chip, comprising at least one redundant signal bond configured for electrical testing using a test fixture; and
at least one final signal bond pad configured for packaging to an interposer,
wherein the at least one redundant signal bond pad and the at least one signal bond pad are coupled to the same signal port.
12 . The integrated circuit chip of claim 11 , wherein the at least one redundant signal bond pad and the at least one final signal bond pad are different sizes.
13 . The integrated circuit chip of claim 11 , wherein the test fixture comprises a probe and the at least one redundant signal bond pad has square-shape, circular-shape, or asymmetrical shape.
14 . The integrated circuit chip of claim 11 , wherein the at least one redundant signal bond pad and the at least one signal bond pad on the chip are formed of a superconducting material.
15 . The integrated circuit chip of claim 11 , wherein the test fixture comprises a probe and the at least one redundant signal bond pad is located such that the probe does not has square-shape, circular-shape, or asymmetrical shape.
16 - 19 . (canceled)
20 . A semiconductor device comprising:
an integrated circuit chip comprising a first signal bond pad and a second signal bond pad connected to the same signal port, wherein the first signal bond pad has a greater lateral width than the second signal bond pad and is configured for testing the chip prior to packaging, and wherein the second signal bond pad is configured for packaging with an interposer or a printed circuit board.
21 . The semiconductor device of claim 20 , wherein the first signal bond pad and the second signal bond pad are of different sizes.
22 . The semiconductor device of claim 20 , wherein the first signal bond pad and the second signal bond pad on the chip are formed of a superconducting material.
23 - 25 . (canceled)