Converting multiple instructions into a single combined instruction with an extension opcode
Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
1. A preprocessing unit for converting program instructions for two-stage processors, the preprocessing unit configured for:
receiving a group of program instructions;
determining that at least two of the group of program instructions can be converted into a single combined instruction;
converting the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction, wherein the format indicates which respective bits of the single combined instruction correspond respectively to: an operand, a memory location, and a program instruction of the at least two program instructions; and
sending the single combined instruction to the execution unit.
2. The preprocessing unit of claim 1 , wherein the extension opcode further indicates an operation to perform on an intermediate result of the single combined instruction.
3. The preprocessing unit of claim 1 , wherein a length of the single combined instruction is less than a combined length of the two program instructions.
4. The preprocessing unit of claim 1 , wherein the single combined instruction comprises, unmodified, at least one of the two program instructions.
5. The preprocessing unit of claim 1 , wherein the two program instructions each comprise a reference to a same memory location.
6. The preprocessing unit of claim 1 ,
wherein receiving, by the preprocessing unit, the group of program instructions comprises receiving the group of program instructions within a window of program instructions; and
wherein determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into the single combined instruction comprises searching the window of program instructions for at least two program instructions that include a reference to a same memory location.
7. The preprocessing unit of claim 1 , wherein the single combined instruction is an internal operation instruction.
8. A computing system, the computing system including a preprocessing unit for converting program instructions for two-stage processors, the preprocessing unit configured for:
receiving, by the preprocessing unit, a group of program instructions;
determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction;
converting the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction, wherein the format indicates which respective bits of the single combined instruction correspond respectively to: an operand, a memory location, and a program instruction of the at least two program instructions; and
sending, by the preprocessing unit, the single combined instruction to the execution unit.
9. The computing system of claim 8 , wherein the extension opcode further indicates an operation to perform on an intermediate result of the single combined instruction.
10. The computing system of claim 8 , wherein a length of the single combined instruction is less than a combined length of the two program instructions.
11. The computing system of claim 8 , wherein the single combined instruction comprises, unmodified, at least one of the two program instructions.
12. The computing system of claim 8 , wherein the two program instructions each comprise a reference to a same memory location.
13. The computing system of claim 8 ,
wherein receiving, by the preprocessing unit, the group of program instructions comprises receiving the group of program instructions within a window of program instructions; and
wherein determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into the single combined instruction comprises searching the window of program instructions for at least two program instructions that include a reference to a same memory location.